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Speedup evaluation of HEVC parallel video coding using Tiles

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Abstract

This paper presents an extensive evaluation of the HEVC parallel video coding when using Tiles. The evaluation consists on finding the tiling pattern that yields the maximum possible speedup for a set of video sequences considering several encoding parameters, measuring the coding efficiency variation of using such tiling pattern instead of the uniform tiling pattern, and calculating how far from the uniform tiling the maximum speedup tiling pattern is. To perform these evaluations, a different number of Tiles with different tiling patterns are applied; apart from that, different encoding profiles are employed. The results show that the speedup yielded by the uniform tiling is highly dependent on the video sequence and employed encoding profile. When encoding a set of video sequences with the same encoding parameters, the greater speedup may be up to 25% higher than the minor speedup, whereas when encoding the same video sequence with different encoding profiles, the greater speedup may be up to 21% higher than the minor speedup. When applying the maximum speedup tiling pattern to an encoding, distinct speedup gains may be achieved. While for some video sequences the maximum possible speedup equals the speedup yielded by the uniform tiling pattern, for others, changing from the uniform tiling to a better one may result in more than 40% of speedup gain. The results also show that when changing from the uniform tiling pattern to one that results in the maximum possible speedup, the coding efficiency variation is negligible; therefore, it is rewarding to seek better tiling patterns.

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Acknowledgements

This study was financed in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior—Brasil (CAPES)—Finance Code 001, Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq), and Fundação de Amparo à pesquisa do Estado do Rio Grande do Sul Brasil (FAPERGS).

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  1. Video Technology Research Group (ViTech), Graduate Program in Computer Science (PPGC), Federal University of Pelotas (UFPel), Pelotas, Brazil

    Iago Storch, Daniel Palomino, Bruno Zatt & Luciano Agostini

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  1. Iago Storch
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  2. Daniel Palomino
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  4. Luciano Agostini
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Correspondence to Iago Storch.

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Storch, I., Palomino, D., Zatt, B. et al. Speedup evaluation of HEVC parallel video coding using Tiles. J Real-Time Image Proc 17, 1469–1486 (2020). https://doi.org/10.1007/s11554-019-00900-y

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  • DOI: https://doi.org/10.1007/s11554-019-00900-y

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