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A memory and area-efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 DWT filters for real-time image decomposition

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Abstract

In this article, we have proposed the internal architecture of a dedicated hardware for 1D/2D convolution-based 9/7 and 5/3 DWT filters, exploiting bit-parallel ‘distributed arithmetic’ (DA) to reduce the computation time of our proposed DWT design while retaining the area at a comparable level to other recent existing designs. Despite using memory extensive bit-parallel DA, we have successfully achieved 90% reduction in the memory size than that of the other notable architectures. Through our proposed architecture, both the 9/7 and 5/3 DWT filters can be realized with a selection input, mode. With the introduction of DA, we have incorporated pipelining and parallelism into our proposed convolution-based 1D/2D DWT architectures. We have reduced the area by 38.3% and memory requirement by 90% than that of the latest remarkable designs. The critical-path delay of our design is almost 50% than that of the other latest designs. We have successfully applied our prototype 2D design for real-time image decomposition. The quality of the architecture in case of real-time image decomposition is measured by ‘peak signal-to-noise ratio’ and ‘computation time’, where our proposed design outperforms other similar kind of software- and hardware-based implementations.

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  1. Electronics and Telecommunication Engineering Department, Indian Institute of Engineering Science and Technology, Shibpur, Howrah, India

    Anirban Chakraborty & Ayan Banerjee

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  1. Anirban Chakraborty
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  2. Ayan Banerjee
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Correspondence to Anirban Chakraborty.

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Chakraborty, A., Banerjee, A. A memory and area-efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 DWT filters for real-time image decomposition. J Real-Time Image Proc 17, 1421–1446 (2020). https://doi.org/10.1007/s11554-019-00901-x

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