Skip to main content
SpringerLink
Log in

HPP controller: a system controller for high performance computing

  • Research Article
  • Published:
Frontiers of Computer Science in China Aims and scope Submit manuscript

Abstract

This paper introduces the design of a hyper parallel processing (HPP) controller, which is a system controller used in heterogeneous high performance computing systems. It connects several heterogeneous processors via HyperTransport (HT) interfaces, a commercial Infiniband HCA card with PCI-express interface, and a customized global synchronization network with self-defined high-speed interface. To accelerate intra-node communication and synchronization, global address space is supported and some dedicated hardware is integrated in the HPP controller to enable intra-node memory and shared I/O resources. On the prototype system with the HPP controller, evaluation results show that the proposed design achieves high communication efficiency, and obvious acceleration to synchronization operations.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Sun N H, Li K, Chen M Y. HPP: an architecture for high performance and utility computing. Chinese Journal of Computers, 2008, 31(9): 1503–1508

    Article  Google Scholar 

  2. Charlesworth A, Aneshansley N, Haakmeester M, et al. The Starfire SMP Interconnect. In: Proceedings of the 1997 ACM/IEEE Conference on Supercomputing, 1997

  3. Laudon J, Lenoski D. The SGI origin: a ccNUMA highly scalable server. In: Proceedings of the 24th annual International Symposium on Computer Architecture. 1997, 241–251

  4. Agarwal A, Bianchini R, Chaiken D, et al. The MIT Alewife machine: architecture and performance. In: Proceedings of 22nd Annual International Symposium on Computer architecture. 1995, 2–13

  5. Scott S L. Synchronization and communication in the T3E multiprocessor. In: Proceedings of the 7th international conference on architectural support for programming languages and operating systems, Cambridge, Massachusetts, United States. 1996, 26–36

  6. Gara A, Blumrich M A, Chen D, et al. Overview of the Blue Gene/L system architecture. IBM Journal of Research and Development, 2005, 49(2): 195–212

    Article  Google Scholar 

  7. Cao Z, Xu J, Chen M, et al. HPPNetSim: a parallel simulation of large-scale interconnection network. In: Proceedings of 42nd Annual Simulation Symposium. 2009

  8. Li Q, Zhang P, Sun N. HPP-Controller: an intra-node controller designed for connecting heterogeneous CPUs. In: Proceedings of 2009 Cluster Computing and Workshops. 2009, 1–4

  9. Zhu W, Sreedhar V C, Hu Z, et al. Synchronization state buffer: supporting efficient fine-grain synchronization on many-core architectures. In: Proceedings of 34th International Symposium on Computer Architecture. San Diego, California, USA, 2007, 35–45

  10. Chen D K, Su H M, Yew P C. The impact of synchronization and granularity on parallel systems. In: Proceedings of 17th Annual International Symposium on Computer Architecture. 1990, 239–248

  11. Kranz D, Lim B H, Agarwal A. Low-cost support for fine-grain sychronization in multiprocessors. Technical Report: TM-470, 1992, Massachusetts Institute of Technology Cambridge, MA, USA. http://portal.acm.org/citation.cfm?id=889592

    Google Scholar 

  12. Byrd G T, Flynn M J. Producer-consumer communication in distributed shared memory multiprocessors. Proceedings of the IEEE, 1999, 87(3): 456–466

    Article  Google Scholar 

  13. Vlassov V, Merino O, Moritz, C, et al. Support for fine-grained synchronization in shared-memory multiprocessors. In: Proceedings of 9th International Conference on Parallel Computing Technologies. 2007, 453–467

  14. Fide S, Jenks S. Architecture optimizations for synchronization and communication on chip multiprocessors. In: Proceedings of IEEE International Symposium on Parallel and Distributed Processing. 2008

  15. Yu L, Liu Z Y, Fan D R, et al. Study on fine-grained synchronization in many-core architecture. In: Proceedings of 10th ACIS International Conference on Software Engineering, Artificial Intelligences, Networking and Parallel/Distributed Computing. 2009, 524–529

  16. Chiou, D, Ang, B, Greiner R, et al. StartT-NG: delivering seamless parallel computing. In: Proceedings of EURO-PAR’95 Parallel Processing. 1995, 101–116

  17. Mellor-Crummey J, Scott M L. Algorithms for scalable synchronization on shared-memory multiprocessors. ACM Transactions on Computer Systems, 1991, 9(1): 21–65

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100190, China

    Fei Chen, Zheng Cao, Kai Wang, Xuejun An & Ninhui Sun

Authors
  1. Fei Chen
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Zheng Cao
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Kai Wang
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Xuejun An
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Ninhui Sun
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Fei Chen.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Chen, F., Cao, Z., Wang, K. et al. HPP controller: a system controller for high performance computing. Front. Comput. Sci. China 4, 456–465 (2010). https://doi.org/10.1007/s11704-010-0382-y

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11704-010-0382-y

Keywords

Search

Navigation