Abstract
High-performance supercomputers generally comprise millions of CPUs in which interconnection networks play an important role to achieve high performance. New design paradigms of dynamic on-chip interconnection network involve a) topology b) synthesis, modeling and evaluation c) quality of service, fault tolerance and reliability d) routing procedures. To construct a dynamic highly fault tolerant interconnection networks requires more disjoint paths from each source-destination node pair at each stage and dynamic rerouting capability to use the various available paths effectively. Fast routing and rerouting strategy is needed to provide reliable performance on switch/link failures. This paper proposes two new architecture designs of fault tolerant interconnection networks named as reliable interconnection networks (RIN-1 and RIN-2). The proposed layouts are multipath multi-stage interconnection networks providing four disjoint paths for all the source-destination node pairs with dynamic rerouting capability. The designs can withstand switch failures in all the stages (including input and output stages) and provide more reliability. Reliability analysis of various MIN architectures is evaluated. On comparing the results with some existing MINs it is evident that the proposed designs provides higher reliability values and fault tolerance.
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The authors would like to thank the editor and anonymous reviewers whose helpful comments improved the quality of this paper. The author would also like to thank Professors of Reliability Engineering Centre, IIT Kharagpur for their support and suggestions.
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Rajkumar, S., Goyal, N.K. Reliable multistage interconnection network design. Peer-to-Peer Netw. Appl. 9, 979–990 (2016). https://doi.org/10.1007/s12083-015-0368-5
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DOI: https://doi.org/10.1007/s12083-015-0368-5