Abstract
Due to the cost, power requirements and capacity, data are mainly stored off-chip rather than on-chip in embedded systems. The data exchanged between the processor and off-chip memory might be sensitive, security and efficiency of off-chip memory is a major concern in embedded systems. However, existing protection solutions often require significant overhead to achieve adequate protection. This paper proposes a security management method which can guarantee stronger data confidentiality and integrity with a reduced overhead in area, memory footprint, and performance cost. To reduce on-chip memory consumption and latency cost, protection scheduling and storage strategy are carefully studied, then our security management architecture is formed. Afterwards, confidentiality and integrity modules are designed respectively. Data confidentiality is protected through a Binary Additive Stream Cipher-AES-Time Stamp based on circuit and addresses scrambling network of Benes, and data integrity is safeguarded through an integrity checking module based on SHA3-TAH and MSet-XOR-Hash tree. Hardware implementation is designed and synthesized in a 0.18 µm process. The experiment area is about 1.1 mm2 while frequency reaches 563 MHz. The attack complexity is more than 2224 while additional storage consumption is limited in about 26.6%.
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The authors thank all the reviewers and editors for their valuable comments and works. This paper is supported by the National Natural Science Foundation of China (no. 61772550).
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Su, Y., Shen, JW. & Zhang, MQ. A high security and efficiency protection of confidentiality and integrity for off-chip memory. J Ambient Intell Human Comput 10, 2633–2643 (2019). https://doi.org/10.1007/s12652-018-0939-4
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DOI: https://doi.org/10.1007/s12652-018-0939-4