Abstract
The increasing test data volume is considered as a biggest challenge in circuit under test. This challenge leads to higher computational complexity associated with the testing circuits. To reduce the testing time and addresses the problem related to high overhead, high fault coverage andincreased power dissipationmethod is used in system-on-chip (SoC). A new test compression method called divide and compress (D&C) lossless compression coder with Discrete Cosine Transformis used to enhance the compression capability. This framework of D&C lossless compression coder combines the lossless and lossy compression methods. The Discrete Cosine Transform (DCT) manipulates each data bit inside file and this reduces the file size without any data loss after decoding to lossless compression.Depending on the data characteristic, the compression of data is done without any loss in data. Further, the decompression is attained using advanced Finite State Machine (FSM) to reduce overhead. The experimental results on large benchmark circuits like ITC’99 and ISCAS’99 proves that the proposed D&C lossless compression attains reduced testing time and better compression ratio. Further, itlays only soft burden on the hardware.
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04 July 2022
This article has been retracted. Please see the Retraction Notice for more detail: https://doi.org/10.1007/s12652-022-04284-z
References
Chandra A, Chakrabarty K (2001) System-on-a-chip test-data compression and decompression architectures based on Golomb codes. IEEE Trans Comput Aided Des Integr Circuits Syst 20(3):355–368
Chandra A, Chakrabarty K (2002) Reduction of SOC test data volume, scan power and testing time using alternating run-length codes. In: Proceedings of the 39th annual design automation conference (pp. 673–678). ACM.
Chandra A, Chakrabarty K (2003a) A unified approach to reduce SOC test data volume, scan power and testing time. IEEE Trans Comput Aided Des Integr Circuits Syst 22(3):352–363
Chandra A, Chakrabarty K (2003b) Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes. IEEE Trans Comput 52(8):1076–1088
Czysz D, Kassab M, Lin X, Mrugalski G, Rajski J, Tyszer J (2009) Low-power scan operation in test compression environment. IEEE Trans Comput Aided Des Integr Circuits Syst 28(11):1742–1755
Di Martino F, Sessa S (2019) Multi-level fuzzy transforms image compression. J Ambient Intell Human Comput 10(7):2745–2756
El-Maleh AH (2008) Test data compression for system-on-a-chip using extended frequency-directed run-length code. IET Comput Digital Tech 2(3):155–163
Gonciari P, Al-Hashimi B, Nicolici N (2002) Improving compression ratio, area overhead, and test application time for system-on-a-chip test data compression/decompression. In: Proceedings of the conference on design, automation and test in Europe (pp. 604). IEEE Computer Society.
Gonciari PT, Al-Hashimi BM, Nicolici N (2003) Variable-length input Huffman coding for system-on-a-chip test. IEEE Trans Comput Aided Des Integr Circuits Syst 22(6):783–796
Jas A, Ghosh-Dastidar J, Ng ME, Touba NA (2003) An efficient test vector compression scheme using selective Huffman coding. IEEE Trans Comput Aided Des Integr Circuits Syst 22(6):797–806
Kasban H, Hashima S (2019) Adaptive radiographic image compression technique using hierarchical vector quantization and Huffman encoding. J Ambient Intell Human Comput 10(7):2855–2867
Kavousianos X, Kalligeros E, Nikolos D (2008) Multilevel-Huffman test-data compression for IP cores with multiple scan chains. IEEE Trans Very Large Scale Integration (VLSI) Syst 16(7):926–931.
Lee J, Touba NA (2007) LFSR-reseeding scheme achieving low-power dissipation during test. IEEE Trans Comput Aided Des Integr Circuits Syst 26(2):396–401
Lee LJ, Tseng WD, Lin RB, Chang CH (2012) $2^{n} $ pattern run-length for test data compression. IEEE Trans Comput Aided Des Integr Circuits Syst 31(4):644–648
Lin CY, Lin HC, Chen HM (2010) On reducing test power and test volume by selective pattern compression schemes. IEEE Trans Very Large Scale Integration (VLSI) Syst 18(8):1220–1224
Qin, D. (2019). A compression and transmission method for surveillance video data using SPICE protocol and DWT in cloud desktop environment. J Ambient Intell Human Comput, 1–9.
Rosinger P, Gonciari PT, Al-Hashimi BM, Nicolici N (2001) Simultaneous reduction in volume of test data and power dissipation for systems-on-a-chip. Electron Lett 37(24):1434–1436
Ruan X, Katti R (2006) An efficient data-independent technique for compressing test vectors in systems-on-a-chip. In: Emerging VLSI technologies and architectures, 2006. IEEE computer society annual symposium on (pp. 6-pp). IEEE.
Ruan X, Katti RS (2007) Data-independent pattern run-length compression for testing embedded cores in SoCs. IEEE Trans Comput 56(4):545–556
Sivanantham S, Padmavathy M, Gopakumar G, Mallick PS, Perinbam JRP (2014) Enhancement of test data compression with multistage encoding. Integration VLSI J 47(4):499–509
Tenentes V, Kavousianos X (2013) High-quality statistical test compression with narrow ATE interface. IEEE Trans Comput Aided Des Integr Circuits Syst 32(9):1369–1382
Touba NA (2006) Survey of test vector compression techniques. IEEE Des Test Comput 23(4):294–303
Tseng WD, Lee LJ (2010) Test data compression using multi-dimensional pattern run-length codes. J Electron Test 26(3):393–400
UmaMaheswari S, SrinivasaRaghavan V (2020) Lossless medical image compression algorithm using tetrolet transformation. J Ambient Intell Human Comput, 1–9.
Yuan H, Mei J, Sun X, Cheng KT, Guo K (2015) A power efficient test data compression method on count compatible PRL coding. J Circ Syst Comput 24(06):1550084
Zhan W, El-Maleh A (2009). A new collaborative scheme of test vector compression based on equal-run-length coding (ERLC). In: Computer supported cooperative work in design, 2009. CSCWD 2009. 13th international conference on (pp 21–25). IEEE.
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This article has been retracted. Please see the retraction notice for more detail: https://doi.org/10.1007/s12652-022-04284-z
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Prema, N.K., Sivaram, M. & Kousik, N.V. RETRACTED ARTICLE: Divide and compress discrete cosine lossless compression coder to reduce dimensionality of test data. J Ambient Intell Human Comput 12, 5817–5824 (2021). https://doi.org/10.1007/s12652-020-02124-6
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DOI: https://doi.org/10.1007/s12652-020-02124-6