Skip to main content
Log in

Flip–flop selection for partial enhance scan chain using DTESFF for high transition delay fault coverage

  • Original Article
  • Published:
International Journal of System Assurance Engineering and Management Aims and scope Submit manuscript

Abstract

In nanometric technologies, testing of delay faults in the integrated circuits is becoming mandatory during manufacturing test. Delay fault testing involves two test vectors. Scan based designs is used for delay fault testing with architectural limitations of traditional scan limits the two pattern delay tests that can be applied to a design which results in degraded delay test coverage. Transition delay fault (TDF) coverage improves appreciably by the use of enhanced scan design as it solves the problem by supporting arbitrary delay test vector pairs at the cost of high area overhead. It also needs fast hold signal which is analogous to scan enable signal as in case of LOS testing. Delay testable enhanced scan flip–flop (DTESFF) has been proposed as a low cost DFT technique to achieve high TDF coverage using enhanced scan design without the need of fast hold signal. In this work, a partial DTESFF scheme augments few scan flip–flops with the DTESFF design by choosing scan flip–flops carefully. It attains most of the TDF coverage advantages of a full DTESFF design with reduced area overhead. Significant improvement in TDF coverage for partial enhance scan using DTESFF has been seen on ISCAS’ 89 benchmark circuits.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8

Similar content being viewed by others

References

  • Abraham J, Goel U, Kumar A (2006) Multi-cycle sensitizable transition delay faults. In: Proceedings of VLSI test symposium, pp 306–311

  • Bushnell ML, Agrawal VD (2000) Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits. Springer, New York

  • Cheng K-T et al (1991) A partial enhanced scan approach to robust delay-fault test generation for sequential circuits. In: Proceedings of international test conference, pp 403–410

  • Chao H, Singh AD, Singh V (2011) Efficient partial enhanced scan for high coverage delay testing. In: Proceeding of IEEE 43rd southeastern symposium on system theory (SSST), pp 243–248

  • Deepak KG, Reyna R, Singh V, Singh AD (2009) Leveraging partially enhanced scan for improved observability in delay fault testing. In: Asian test symposium ATS 2009, pp 237–240

  • Devtaprasanna N, Gunda A, Krishnamurthy P, Reddy SM, Pomeranz I (2005) Methods for improving transition delay fault coverage using broadside tests. In: Proceedings of international test conference, pp 256–265

  • EEDesign Article (2002) Delay-fault testing mandatory, author claims, Dec. http://www.eedesign.com/story/OEG20021204S0029. Accessed Jan 2011

  • EETimes Article (2003) Scan-based transition-fault test can do job, Oct. http://www.eetimes.com/story/OEG20031024S0028. Accessed Jan 2011

  • Hawkins C, Keshavarzi A, Segura J (2003) A view from the bottom: Nanometer technology AC parametric failures—why, where, and how to detect. In: Proceedings of international symposium on defect fault tole, pp 267–276

  • Hurst JP, Kanopoulos N (1995) Flip–flop sharing in standard scan path to enhance delay fault testing of sequential circuits. In: Proceedings Asian test symposium, pp 346–352

  • Kumar R, Bollapalli KC, Garg R, Soni T, Khatri SP (2009) A robust pulsed flip–flop and its use in enhanced scan design, IEEE international conference on computer design (ICCD), pp 97–102

  • Lin CJ, Reddy SM (1987) On delay fault testing in logic circuits. IEEE Trans Comput Aided Des Integr Circuits Syst 6(5):694–703

    Article  Google Scholar 

  • Mak T, Krstic A, Cheng KT, Wang LC (2004) New challenges in delay testing of nanometer, multigigahertz designs. IEEE Des Test Comput 21(3):241–247

    Article  Google Scholar 

  • Namba K, Ikeda T, Ito H (2010) Construction of SEU tolerant flip–flops allowing enhanced scan delay fault testing. IEEE Trans Very Large Scale Integr VLSI Syst 18(9):1265–1276

    Article  Google Scholar 

  • Nassif S (2000) Delay variability: sources, impacts and trends. In: Proceedings of international solid state circuits conference, pp 368–369

  • Patil S, Savir J (1992) Skewed-load transition test: part II, coverage. In: Proceedings of international test conference, p 714

  • Pei S, Li H, Li X (2011) Flip–flop selection for partial enhanced scan to reduce transition test data volume. IEEE Trans Very Large Scale Integr VLSI Syst PP(99):1–13

    Google Scholar 

  • Savir J (1992) Skewed-load transition test: part I, calculus. In: Proceedings of international test conference, p 705

  • Savir J, Patil S (1994) On broad-side delay test. Very Large Scale Integration (VLSI) Systems 2, 368

  • Saxena J, Butler KM, Gatt J, Raghuraman R, Kumar SP, Basu S, Campbell DJ, Berech J (2002) Scan-based transition fault testing—implementation and low cost test challenges. In: Proceedings of international test conference, pp 1120–1129

  • Seongmoon W, Xiao L, Chakradhar ST (2004) Hybrid delay scan: a low hardware overhead scan-based delay test technique for high fault coverage and compact test sets. In: Proceedings of design, automation and test in Europe, pp 1296–1301

  • Suhag AK, Shrivastava V (2011) Delay testable enhanced scan flip–flop: DFT for high fault coverage. In: Proceedings of international symposium on electronic system design (ISED), pp 129–133

  • Suhag AK, Shrivastava V (2012) Performance evaluation of delay testable enhanced scan flip–flop. Int J Syst Assur Eng Manag 3(3):169–174

    Article  Google Scholar 

  • TekuMalla RC et al (1997) Delay testing with clock control: an alternative to enhanced scan. In: Proceedings of international test conference, pp 454–462

  • Waicukauski JA, Lindbloom E, Rosen B, Iyengar V (1987) Transition fault simulation. IEEE Des Test Comput 4:32–38

    Article  Google Scholar 

  • Wang S, Wei W (2008) Low overhead partial enhanced scan technique for compact and high fault coverage transition delay test patterns. In: Proceedings of European test symposium, pp 125–130

  • Wang S, Liu X, Chakradhar ST (2004) Hybrid delay scan: a low hardware overhead scan-based delay test technique for high fault coverage and compact test sets. In: Proceedings of design, automation and test in Europe, pp 1296–1301

  • Xu G, Singh AD (2006) Low cost launch-on-shift delay test with slow scan enable. In: Proceedings of European test symposium, pp 9–14

  • Xu G, Singh AD (2007) Achieving high transition delay fault coverage with partial DTSFF Scan Chains. In: Proceedings of international test conference, pp 1–9

  • Zhang Z, Reddy SM, Pomeranz I, Lin X, Rajski J (2006) Scan tests with multiple fault activation cycles for delay faults. In: Proceedings of VLSI test symposium, pp 343–348

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Vivek Shrivastava.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Suhag, A.K., Shrivastava, V. & Singh, N. Flip–flop selection for partial enhance scan chain using DTESFF for high transition delay fault coverage. Int J Syst Assur Eng Manag 4, 303–311 (2013). https://doi.org/10.1007/s13198-013-0170-9

Download citation

  • Received:

  • Revised:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s13198-013-0170-9

Keywords

Navigation