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Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags

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Abstract

An important challenge associated with the current massive deployment of Radio Frequency Identification solutions is to provide security to passive tags while meeting their micro Watt power budget. This can either be achieved by designing new lightweight ciphers, or by proposing advanced low-power implementations of standard ciphers. In this paper, we show that the AES algorithm can fit into this micro Watt power budget by combining ultra-low-voltage implementations with a proper selection of the process flavor in a low-cost nanometer CMOS technology. Interestingly, this approach only requires slight modifications to the standard EDA tool flow, without incurring the engineering costs of architecture optimizations. In order to demonstrate this claim, we successfully designed and manufactured an AES coprocessor in a 65 nm low-power CMOS process. We prove with measurement results obtained from a set of 20 manufactured dies that the proposed coprocessor can be safely operated down to 0.32 V with an energy per 128-bit encryption/decryption at least 2.75× lower than in previously published low-power AES implementations.

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References

  1. Barnett, R., Balachandran, G., Lazar, S., Kramer, B., Konnail, G., Rajasekhar, S., Drobny, V.: A passive UHF RFID transponder for EPC Gen 2 with-14dbm sensitivity in 0.13 μm CMOS. In: IEEE International Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers, pp. 582–623. IEEE (2007)

  2. Batina, L., Guajardo, J., Kerins, T., Mentens, N., Tuyls, P., Verbauwhede, I.: An elliptic curve processor suitable for RFID-tags. IACR (2006, eprint)

  3. Bertoni, G., Macchetti, M., Negri, L., Fragneto, P.: Power-efficient ASIC synthesis of cryptographic sboxes. In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI, p. 281. ACM (2004)

  4. Bogdanov, A., Knudsen, L.R., Leander, G., Paar, C., Poschmann, A., Robshaw, M.J.B., Seurin, Y., Vikkelsoe, C.: Present: an ultra-lightweight block cipher. In: Paillier, P., Verbauwhede, I. (eds.) 9th International Workshop on Cryptographic Hardware and Embedded Systems—CHES 2007. Lecture Notes in Computer Science, vol. 4727, pp. 450–466. Springer, Berlin (2007)

  5. Bol, D., Ambroise, R., Flandre, D., Legat, J.: Analysis and minimization of practical energy in 45 nm subthreshold logic circuits. In: IEEE International Conference on Computer Design, 2008. ICCD 2008, pp. 294–300. IEEE (2008)

  6. Bol D., Ambroise R., Flandre D., Legat J.: Interests and limitations of technology scaling for subthreshold logic. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17(10), 1508–1519 (2009)

    Article  Google Scholar 

  7. Bol, D., Flandre, D., Legat, J.: Technology flavor selection and adaptive techniques for timing-constrained 45 nm subthreshold circuits. In: Proceedings of the 14th ACM/IEEE International Symposium on Low power Electronics and Design, pp. 21–26. ACM (2009)

  8. Bol, D., Hocquet, C., Flandre, D., Legat, J.: The Detrimental Impact of Negative Celsius Temperature on Ultra-Low-Voltage CMOS Logic. In: European Solid-State Circuits Conference ESSCIRC (2010)

  9. Calhoun B., Wang A., Chandrakasan A.: Modeling and sizing for minimum energy operation in subthreshold circuits. IEEE J. Solid State Circuits 40(9), 1778–1786 (2005)

    Article  Google Scholar 

  10. Canright, D.: A very compact S-Box for AES. In: Rao, J.R., Sunar, B. (eds.) Cryptographic Hardware and Embedded Systems—CHES 2005. Lecture Notes in Computer Science, vol. 3659, pp. 441–455. Springer, Berlin (2005)

  11. Cho, N., Song, S.J., Kim, S., Kim, S., Yoo, H.J.: A 5.1 μW UHF RFID tag chip integrated with sensors for wireless environmental monitoring. In: Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005, pp. 279–282 (2005)

  12. Das, R., Harrop, P.: RFID forecasts, players and opportunities 2011–2021. IDTechEx Report (2010)

  13. Feldhofer, M., Wolkerstorfer, J.: Strong crypto for RFID tags—a comparison of low-power hardware implementations. In: IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, pp. 1839–1842. IEEE (2007)

  14. Feldhofer M., Wolkerstorfer J., Rijmen V.: AES implementation on a grain of sand. IEE Proc. Inf. Secur. 152(1), 13–20 (2005)

    Article  Google Scholar 

  15. Finchelstein, D., Sze, V., Sinangil, M., Koken, Y., Chandrakasan, A.: A low-power 0.7-V H. 264 720p video decoder. In: IEEE Asian Solid-State Circuits Conference, 2008. A-SSCC’08, pp. 173–176. IEEE (2008)

  16. Good, T., Benaissa, M.: 692-nW Advanced Encryption Standard (AES) on a 0.13 μm. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (99), 1 (2009)

  17. Hamalainen, P., Alho, T., Hannikainen, M., Hamalainen, T.: Design and implementation of low-area and low-power aes encryption hardware core. In: 9th EUROMICRO Conference on Digital System Design, pp. 577–583. IEEE (2006)

  18. Hempstead, M., Wei, G., Brooks, D.: Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations. In: Proceedings of the 2006 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, pp. 368–378. ACM (2006)

  19. Hong, Y., Chan, C.F., Guo, J., Ng, Y.S., Shi, W., Leung, L.K., Leung, K.N., Choy, C.S., Pun, K.P.: Design of passive UHF RFID tag in 130 nm CMOS technology. In: IEEE Asia Pacific Conference on Circuits and Systems, 2008. APCCAS 2008, pp. 1371 –1374 (2008)

  20. EPCglobal Inc.: EPC Radio-Frequency Identity Protocols Class-1 Generation-2 UHF RFID Protocol for Communications at 860 MHz–960 MHz Version 1.2.0 (2008). http://www.gs1.org/

  21. Juels A.: RFID security and privacy: a research survey. IEEE J. Sel. Areas Commun. 24(2), 381–394 (2006)

    Article  MathSciNet  Google Scholar 

  22. Kamel, D., Standaert, F., Flandre, D.: Scaling trends of the AES S-Box low power consumption in 130 and 65 nm CMOS technology nodes. In: IEEE International Symposium on Circuits and Systems, 2009. ISCAS 2009, pp. 1385–1388. IEEE (2009)

  23. Kim T., Keane J., Eom H., Kim C.: Utilizing reverse short-channel effect for optimal subthreshold circuit design. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 15(7), 821–829 (2007)

    Article  Google Scholar 

  24. Kitsos P., Zhang Y.: RFID Security—Techniques, Protocols and System-on-Chip Design. Springer, Berlin (2008)

    Google Scholar 

  25. Kwong, J., Chandrakasan, A.: Variation-driven device sizing for minimum energy sub-threshold circuits. In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, pp. 8–13. ACM (2006)

  26. Leander, G., Paar, C., Poschmann, A., Schramm, K.: New lightweight DES variants. In: Fast Software Encryption, pp. 196–210. Springer, Berlin (2007)

  27. Mentens, N., Batina, L., Preneel, B., Verbauwhede, I.: A systematic evaluation of compact hardware implementations for the Rijndael S-box. Topics in Cryptology—CT-RSA 2005, pp. 323–333 (2005)

  28. Moore G. et al.: Cramming more components onto integrated circuits. Proc. IEEE 86(1), 82–85 (1998)

    Article  Google Scholar 

  29. Poschmann, A.: Lightweight cryptography—cryptographic engineering for a pervasive world. Cryptology ePrint Archive, Report 2009/516 (2009). http://eprint.iacr.org/

  30. Pu, Y., de Gyvez, J., Corporaal, H., Ha, Y.: An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply. In: IEEE International Solid-State Circuits Conference. ISSCC 2009. Digest of Technical Papers, pp. 146–147. IEEE (2009)

  31. Satoh, A., Morioka, S., Takano, K., Munetoh, S.: A Compact Rijndael Hardware Architecture with S-Box Optimization. In: Proceedings of ASIACRYPT 2001. LNCS, vol. 2248, pp. 239–254 (2000)

  32. Soeleman, H., Roy, K.: Ultra-low power digital subthreshold logic circuits. In: Proceedings of the 1999 International Symposium on Low Power Electronics and Design, pp. 94–96. ACM (1999)

  33. Sridhara, S., DiRenzo, M., Lingam, S., Lee, S., Blazquez, R., Maxey, J., Ghanem, S., Lee, Y., Abdallah, R., Singh, P., et al.: Microwatt embedded processor platform for medical system-on-chip applications. In: IEEE Symposium on VLSI Circuits (VLSIC), 2010, pp. 15–16. IEEE (2010)

  34. National Institute of Standards Technology (NIST): Announcing the Advanced Encryption Standard AES. Federal Information Processing Standards Publication 197 (2001)

  35. Sze, V., Chandrakasan, A.: A 0.4-V UWB baseband processor. In: Proceedings of the 2007 International Symposium on Low power Electronics and Design, pp. 262–267. ACM, New York (2007)

  36. Verma N., Kwong J., Chandrakasan A.: Nanometer MOSFET variation in minimum energy subthreshold circuits. IEEE Trans. Electron. Dev. 55(1), 163–174 (2007)

    Article  Google Scholar 

  37. Want R.: An introduction to RFID technology. Pervasive Comput. 5(1), 25–33 (2006)

    Article  Google Scholar 

  38. Yeager D., Zhang F., Zarrasvand A., George N., Daniel T., Otis B.: A 9 μA, Addressable Gen2 Sensor Tag for Biosignal Acquisition. IEEE J. Solid State Circuits 45(10), 2198–2209 (2010)

    Article  Google Scholar 

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Correspondence to Cédric Hocquet.

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Hocquet, C., Kamel, D., Regazzoni, F. et al. Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags. J Cryptogr Eng 1, 79–86 (2011). https://doi.org/10.1007/s13389-011-0005-z

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  • DOI: https://doi.org/10.1007/s13389-011-0005-z

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