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Reducing risks through simplicity: high side-channel security for lazy engineers

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Abstract

Countermeasures against side-channel attacks are in general expensive, and a lot of research has been devoted to the optimization of their security versus performance trade-off. Besides, a wide literature has also shown that implementing such countermeasures is an error-prone task and requires to deal with various engineering challenges (e.g., physical defaults, compositional errors, ...). This work aims to contribute to this second item, by evaluating the extent to which (almost) key-homomorphic primitives, and in particular a recent PRF instance based on the learning with rounding problem, can lead to easy-to-implement and easier-to-evaluate side-channel-secure designs. We confirm these properties by describing an FPGA implementation that does not require complex (compositional) reasoning in its analysis and can be masked securely under simple design conditions, and for which the evaluation directly scales to arbitrary number of shares. We provide a comprehensive performance and (worst-case) security analysis of our design and compare the obtained results with those of an AES implementation protected with the domain-oriented masking scheme. Results show that simplicity has a cost, which becomes less prohibitive as security requirements increase.

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Notes

  1. While other masking-friendly block ciphers could have been investigated, this open-source AES implementation is representative of the state-of-the-art protected designs. This allows us to draw qualitative trade-offs between the LWR-rekeying scheme and a standard substitution permutation network.

  2. Securing \({\mathsf {corrSk}} (\cdot )\) which is executed by the decryption party can be done with similar means, by increasing the amount of correction information by one bit.

  3. Typically, the first set corresponds to fixed input. The second set can be either chosen to correspond to random inputs or to another fixed input [28]. We detail our selection of inputs for LWR in Sect. 5.2

  4. All the resource utilization results reported are obtained with Xilinx ISE 14.7.

  5. These have a limited impact on the metric for large d. Indeed, they grow linearly with d, while the rest of the circuit is quadratic.

  6. In the following evaluations, it is implemented with two unprotected AES cores delivering 128 bits of randomness every 55 cycles.

  7. The case of an adversary targeting directly the value and not a transition has also been studied. In that case, the information available is much lower. Since we aim at worst-case evaluations, only the results of transition-based attacks are reported.

  8. http://satoh.cs.uec.ac.jp/SAKURA/hardware/SAKURA-X.html.

  9. This (again) calls for a better understanding of the exact requirements for the randomness used in masking schemes.

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Acknowledgements

François-Xavier Standaert is a Senior Research Associate of the Belgian Fund for Scientific Research (FNRS-F.R.S.). This work has been funded in part by the European Union (EU) through the ERC project 724725 (acronym SWORD)

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Authors and Affiliations

  1. ICTEAM Institute, UCLouvain, Louvain-la-Neuve, Belgium

    Olivier Bronchain & François-Xavier Standaert

  2. NXP Semiconductors Austria, Gratkorn, Austria

    Tobias Schneider

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  1. Olivier Bronchain
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Tobias Schneider: The majority of the author’s contribution was performed while he was with ICTEAM Institute, UCLouvain, Louvain-la-Neuve, Belgium.

Appendices

A Leakage model

Linear basis was used as a leakage model. Each of the curves corresponds to a single \(\alpha _i\) showing the activity of each of the bits across time.

Fig. 16
figure 16

Linear basis for LWR leakage model

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B Cost of security

Fig. 17
figure 17

Cost\(\times \)cycles metric versus data complexity for a univariate adversary. Numbers correspond to the number of shares within the implementation

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C Parallelism parameter

Fig. 18
figure 18

Cost\(\times \)cycles metric versus data complexity for a univariate and multivariate adversaries with a linear extrapolation on the noise with P

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Bronchain, O., Schneider, T. & Standaert, FX. Reducing risks through simplicity: high side-channel security for lazy engineers. J Cryptogr Eng 11, 39–55 (2021). https://doi.org/10.1007/s13389-020-00241-8

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