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Reducing Side-Channel Leakage of Encryption Engines Using Integrated Low-Dropout Voltage Regulators

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Abstract

Low-dropout (LDO) regulators are becoming a part of modern processor architectures for fine-grain power management and higher energy efficiency. This paper shows that these integrated LDOs can also be leveraged to enhance side-channel analysis resistance of encryption engines to power side-channel analysis (PSCA) attacks. The current transformation induced by integrated LDOs coupled with limited bandwidth of the feedback loop help suppress the side-channel leakage. The impact of both analog LDO (ALDO) and all-digital LDO (ADLDO) on the load currents is studied with correlation analysis between the load and the LDO input current. The effectiveness of integrated LDOs as countermeasure to PSCA is further explored with Correlation Power Analysis (CPA) and Test Vector Leakage Assessment (TVLA) performed on both simulated as well as measured load currents for a 128-bit Advanced Encryption Standard (AES) implemented in GF-130-nm process technology. We show that integrated LDOs can enhance PSCA resistance; however, the trade-off between integrated LDO performance and side-channel security is essential. We design integrated LDOs optimized for low-power/compact encryption engines and show that LDO-based protection can increase power attack resistance by >800× with minimal power, area, and performance overheads.

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Funding

This material is based on a work supported in part by Intel Corp. and National Science Foundation.

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Authors and Affiliations

  1. Georgia Institute of Technology, Atlanta, GA, USA

    Arvind Singh, Monodeep Kar & Saibal Mukhopadhyay

  2. Intel Corporation, Santa Clara, CA, USA

    Sanu Mathew, Anand Rajan & Vivek De

Authors
  1. Arvind Singh
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  2. Monodeep Kar
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  3. Sanu Mathew
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  4. Anand Rajan
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  5. Vivek De
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  6. Saibal Mukhopadhyay
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Correspondence to Arvind Singh.

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Singh, A., Kar, M., Mathew, S. et al. Reducing Side-Channel Leakage of Encryption Engines Using Integrated Low-Dropout Voltage Regulators. J Hardw Syst Secur 1, 340–355 (2017). https://doi.org/10.1007/s41635-017-0023-0

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  • DOI: https://doi.org/10.1007/s41635-017-0023-0

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