Skip to main content
SpringerLink
Log in

A Survey of Techniques for Improving Security of Non-volatile Memories

  • Published:
Journal of Hardware and Systems Security Aims and scope Submit manuscript

Abstract

Due to their high-density and near-zero leakage power consumption, non-volatile memories (NVMs) are promising candidates for designing future memory systems. However, compared to conventional memories, NVMs also face more severe security threats, e.g., the limited write endurance of NVMs makes them vulnerable to write attacks. Also, the non-volatility of NVMs allows the data to persist even after power-off, which can be accessed by a malicious agent. Further, encryption endangers NVM lifetime and performance by reducing the efficacy of redundant write avoidance techniques. In this paper, we present a survey of techniques for improving security of NVM-based memories by addressing the aforementioned challenges. We highlight the key ideas of the techniques along with their similarities and differences. This paper is expected to be useful for researchers and practitioners in the area of memory and system security.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20
Fig. 21
Fig. 22
Fig. 23

Similar content being viewed by others

References

  1. Mittal S, Vetter J S, Li D (2015) A survey of architectural approaches for managing embedded DRAM and non-volatile on-chip caches. In: IEEE Transactions on parallel and distributed systems (TPDS)

  2. Mittal S, Wang R, Vetter J (2017) DESTINY: a comprehensive tool with 3D and multi-level cell memory modeling capability. In: JLPEA

  3. Seong N H, Woo D H, Lee H -H S (2010) Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping. SIGARCH Comput Archit News 38(3):383–394

    Article  Google Scholar 

  4. Chhabra S, Solihin Y (2010) Defining anomalous behavior for phase change memory. In: Workshop on the use of emerging storage and memory technologies, held in conjunction with HPCA

  5. Mittal S (2016) A survey of techniques for architecting processor components using domain wall memory. ACM J Emerg Technol Comput Syst

  6. Mittal S (2017) A survey of soft-error mitigation techniques for non-volatile memories. Computers 6:8

    Article  Google Scholar 

  7. Mittal S (2016) A survey of architectural techniques for managing process variation. ACM Comput Surv 48 (4):54,1–54,29

    MathSciNet  Google Scholar 

  8. Mittal S, Vetter J S (2016) A survey of software techniques for using non-volatile memories for storage and main memory systems. IEEE Trans Parallel Distrib Syst 27(5):1537–1550

    Article  Google Scholar 

  9. Menezes A J, Van Oorschot P C, Vanstone S A (1996) Handbook of applied cryptography. CRC Press

  10. Qureshi M K, Seznec A, Lastras L A, Franceschini M M (2011) Practical and secure pcm systems by online detection of malicious write streams. In: 2011 IEEE 17th International symposium on high performance computer architecture, pp 478–489

  11. Wu G, Zhang H, Dong Y, Hu J (2012) CAR: securing PCM main memory system with cache address remapping. In: International conference on parallel and distributed systems, pp 628–635

  12. Wu G, Gao J, Zhang H, Dong Y (2011) Improving pcm endurance with randomized address remapping in hybrid memory system. In: International conference on cluster computing, pp 503–507

  13. Mittal S (2016) A survey of power management techniques for phase change memory. Int J Comput Aided Eng Technol (IJCAET) 8(4):424–444

    Article  Google Scholar 

  14. Huang F, Feng D, Xia W, Zhou W, Zhang Y, Fu M, Jiang C, Zhou Y (2016) Security RBSG: protecting phase change memory with security-level adjustable dynamic mapping. In: International parallel and distributed processing symposium (IPDPS), pp 1081–1090

  15. Qureshi M K, Karidis J, Franceschini M, Srinivasan V, Lastras L, Abali B (2009) Enhancing lifetime and security of pcm-based main memory with start-gap wear leveling. In: 2009 42nd Annual IEEE/ACM international symposium on microarchitecture (MICRO), pp 14–23

  16. Mao H, Zhang X, Sun G, Shu J (2017) Protect non-volatile memory from wear-out attack based on timing difference of row buffer hit/miss. In: Design, automation test in Europe conference exhibition (DATE), pp 1623–1626

  17. Haber S, Manadhata P K (2017) Improved security for non-volatile main memory

  18. Chhabra S, Rogers B, Solihin Y, Prvulovic M (2009) Making secure processors os-and performance-friendly. ACM Trans Architect Code Optim (TACO) 5(4):16

    Google Scholar 

  19. Kong J, Zhou H (2010) Improving privacy and lifetime of pcm-based main memory. In: 2010 IEEE/IFIP International conference on dependable systems networks (DSN), pp 333–342

  20. Swami S, Rakshit J, Mohanram K (2016) Secret: smartly encrypted energy efficient non-volatile memories. In: 2016 53nd ACM/EDAC/IEEE design automation conference (DAC), pp 1–6

  21. Young V, Nair P J, Qureshi M K (2015) Deuce: write-efficient encryption for non-volatile memories. SIGARCH Comput Archit News 43(1):33–44

    Article  Google Scholar 

  22. Luo X, Liu D, Liangy L, Li Y, Zhong K, Long L (2015) Mobilock: an energy-aware encryption mechanism for nvram-based mobile devices. In: 2015 IEEE Non-volatile memory system and applications symposium (NVMSA), pp 1–6

  23. Zhang X, Zhang C, Sun G, Di J, Zhang T (2013) An efficient run-time encryption scheme for non-volatile main memory. In: 2013 International conference on compilers, architecture and synthesis for embedded systems (CASES), pp 1–10

  24. Liu C, Yang C (2015) Secure and durable (sedura): an integrated encryption and wear-leveling framework for pcm-based main memory. In: ACM SIGPLAN Notices, vol 50, no. 5.1. ACM, p 12

  25. Huang F, Feng D, Hua Y, Zhou W (2017) A wear-leveling-aware counter mode for data encryption in non-volatile memories. In: Design, automation test in Europe conference exhibition (DATE), pp 910–913

  26. Jalili M, Sarbazi-Azad H (2017) Endurance-aware security enhancement in non-volatile memories using compression and selective encryption. IEEE Trans Comput 66(7):1132–1144

    Article  MathSciNet  MATH  Google Scholar 

  27. Yu H, Du Y (2014) Increasing endurance and security of phase-change memory with multi-way wear-leveling. IEEE Trans Comput 63(5):1157–1168

    Article  MathSciNet  MATH  Google Scholar 

  28. Zhang X, Sun G (2017) Toss-up wear leveling: protecting phase-change memories from inconsistent write patterns. In: Design automation conference, pp 3:1–3:6

  29. Swami S, Mohanram K (2017) Covert: counter overflow reduction for efficient encryption of non-volatlle memories. In: Design, automation test in Europe conference exhibition (DATE), pp 906–909

  30. Zhou W, Feng D, Hua Y, Liu J, Huang F, Zuo P (2016) Increasing lifetime and security of phase-change memory with endurance variation. In: 2016 IEEE 22nd International conference on parallel and distributed systems (ICPADS), pp 861– 868

  31. Seznec A (2010) A phase change memory as a secure main memory. IEEE Comput Archit Lett 9(1):5–8

    Article  Google Scholar 

  32. Zhang H, Zhang C, Zhang X, Sun G, Shu J (2016) Pin tumbler lock: a shift based encryption mechanism for racetrack memory. In: Asia and South Pacific design automation conference (ASP-DAC), pp 354–359

  33. Wang Y, Ni L, Chang C -H, Yu H (2016) DW-AES: a domain-wall nanowire-based AES for high throughput and energy-efficient data encryption in non-volatile memory. IEEE Trans Inf Forensics Secur 11(11):2426–2440

    Article  Google Scholar 

  34. Mittal S, Vetter J S (2014) EqualChance: addressing intra-set write variation to increase lifetime of non-volatile caches. In: 2nd USENIX workshop on interactions of NVM/flash with operating systems and Workloads (INFLOW)

  35. Awad A, Manadhata P, Haber S, Solihin Y, Horne W (2016) Silent shredder: zero-cost shredding for secure non-volatile main memory controllers. SIGOPS Oper Syst Rev 50(2):263–276

    Article  Google Scholar 

  36. Mittal S (2017) A survey of value prediction techniques for leveraging value locality. Concurrency and computation: practice and experience

  37. Chhabra S, Solihin Y (2011) i-NVMM: a secure non-volatile main memory system with incremental encryption. In: 2011 38th Annual international symposium on computer architecture (ISCA), pp 177–188

  38. Enck W, Butler K, Richardson T, McDaniel P, Smith A (2008) Defending against attacks on main memory persistence. In: Computer security applications conference, 2008. ACSAC 2008. IEEE, pp 65–74

  39. Hou F, He H (2015) Ultra simple way to encrypt non-volatile main memory. Secur Commun Netw 8 (7):1155–1168

    Article  Google Scholar 

  40. Yan C, Englender D, Prvulovic M, Rogers B, Solihin Y (2006) Improving cost, performance, and security of memory encryption and authentication. ACM SIGARCH Comput Architect News 34(2):179–190

    Article  Google Scholar 

  41. Schechter S, Loh GH, Straus K, Burger D (2010) Use ECP, not ECC, for hard failures in resistive memories. In: International symposium on computer architecture (ISCA), pp 141–152

  42. Alsalibi A I, Mittal S, Al-betar M A, Sumari P B (2018) A survey of techniques for architecting SLC/MLC/TLC hybrid flash memory based SSDs concurrency and computation practice and experience

  43. Henson M, Taylor S (2014) Memory encryption: a survey of existing techniques. ACM Comput Surv (CSUR) 46(4):53

    Article  MATH  Google Scholar 

  44. Mittal S (2016) A survey of techniques for approximate computing. ACM Comput Surv 48(4):62,1–62,33

    MathSciNet  Google Scholar 

  45. Wang R, Mittal S, Zhang Y, Yang J (2017) Decongest: accelerating super-dense PCM under write disturbance by hot page remapping. IEEE Comput Architect Lett

  46. Seaborn M Exploiting the dram rowhammer bug to gain kernel privileges. https://goo.gl/NMK6MM

  47. Mittal S, Vetter J (2015) A survey of techniques for modeling and improving reliability of computing systems. IEEE Trans Parallel Distrib Syst

  48. Kim W, BrightSky M, Masuda T, Sosa N, Kim S, Bruce R, Carta F, Fraczak G, Cheng H, Ray A et al (2016) ALD-based confined PCM with a metallic liner toward unlimited endurance. In: IEEE International electron devices meeting (IEDM), pp 4–2

  49. Mittal S, Vetter J S (2016) EqualWrites: reducing intra-set write variations for enhancing lifetime of non-volatile caches. IEEE Trans VLSI Syst 24(1):103–114

    Article  Google Scholar 

Download references

Funding

Support for this work was provided by the Science and Engineering Research Board (SERB), India, award number ECR/2017/000622.

Author information

Authors and Affiliations

  1. IIT Hyderabad, E-621, IIT Hyderabad, Khandi, Telangana, 502285, India

    Sparsh Mittal

  2. Israa University, Gaza, Palestine

    Ahmed Izzat Alsalibi

Authors
  1. Sparsh Mittal
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Ahmed Izzat Alsalibi
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Sparsh Mittal.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Mittal, S., Alsalibi, A.I. A Survey of Techniques for Improving Security of Non-volatile Memories. J Hardw Syst Secur 2, 179–200 (2018). https://doi.org/10.1007/s41635-018-0034-5

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s41635-018-0034-5

Keywords

Search

Navigation