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Implementation-Based Design Fingerprinting for Robust IC Fraud Detection

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Abstract

With the global spanning of integrated circuit (IC) and electronic device supply chains, the ability of an untrusted foundry to alter a design for intellectual property (IP)/IC piracy increases. To tackle this threat, this paper proposes a design-based fingerprinting methodology based on machine learning schemes. The proposed method considers the effect of process variations, measurement noise, and device aging. The proposed fingerprinting scheme can identify if the circuit is original or has been altered by an adversary to hide piracy. Changing a gate to an equivalent counterpart does not change the functionality of the circuit and we assess these as altered circuits. Altering the circuit can arise if an adversary gains access to the register-transfer level (RTL) or netlist of a design in an untrusted supply chain or uses the datasheet to implement a functionally equivalent design. Experimentally we determine that our method can detect a pirated chip with near 100% accuracy when classifying new ICs, and above 96% accuracy when classifying at any age up to 7 years in the presence of noise if at least 2.5% of the gates in the IC have been altered by an adversary.

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Acknowledgments

We would like to thank Brien Croteau for his help developing ideas.

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Authors and Affiliations

  1. Department of Computer Science and Electrical Engineering, University of Maryland Baltimore County, Baltimore, MD, USA

    James Shey, Naghmeh Karimi, Ryan Robucci & Chintan Patel

  2. Electrical and Computer Engineering Department, U.S. Naval Academy, Annapolis, MD, USA

    James Shey

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Correspondence to James Shey.

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Shey, J., Karimi, N., Robucci, R. et al. Implementation-Based Design Fingerprinting for Robust IC Fraud Detection. J Hardw Syst Secur 3, 426–439 (2019). https://doi.org/10.1007/s41635-019-00081-x

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