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Understanding Security Threats in Emerging Neuromorphic Computing Architecture

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Abstract

Neuromorphic computing marks the beginning of a new era in computing system design, owing to the introduction of complex and unorthodox non-Von Neumann architectures, in conjunction with new post-CMOS nano-ionic devices. These neuromorphic chips are projected to soon become a mainstay platform for a diverse set of applications, ranging from day-to-day rudimentary decision making, to safety critical defense and healthcare management. In this environment, hardware security can no longer take an auxiliary role in system design. In this work, we lay a solid foundation of understanding the broad security implications of emerging memristor-based neuromorphic computing paradigm. We investigate various security loopholes arising from an untrustworthy neuromorphic design environment. We propose, examine and evaluate the security threats arising from—(a) covert hardware Trojans and (b) external attacks exploiting implementation-specific vulnerabilities. Subsequently, we discuss three specific attacks targeting crucial components of the neuromorphic design and demonstrate how the security breaches in the neuromorphic systems can directly impact the end-user experience. Uncovering these security vulnerabilities in the emerging neuromorphic computing paradigm can be instrumental in shaping our design practices.

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References

  1. Research GV (2017) Artificial intelligence market analysis by solution (hardware, software, services), by technology (deep learning, machine learning, natural language processing, machine vision), by end-use, by region, and segment forecasts, 2014 - 2025. Available: http://www.grandviewresearch.com/industryanalysis/artificial-intelligence-ai-market

  2. Cohen PR, Feigenbaum EA (2014) The handbook of artificial intelligence, vol 3. Butterworth-Heinemann

  3. Haensch W (2017) Scaling is over @ twhat now? In Device Research Conference (DRC), 2017 75th Annual. IEEE. pp 1–2

  4. Rahman F, Shakya B, Xu X, Forte D, Tehranipoor M (2017) Security beyond cmos: Fundamentals, applications, and roadmap. IEEE Trans Very Large Scale Integr VLSI Syst

  5. Davies M, Srinivasa N, Lin T-H, Chinya G, Cao Y, Choday SH, Dimou G, Joshi P, Imam N, Jain S et al (2018) Loihi: A neuromorphic manycore processor with on-chip learning. IEEE Micro 38(1):82–99

    Article  Google Scholar 

  6. Benjamin BV, Gao P, McQuinn E, Choudhary S, Chandrasekaran AR, Bussat JM, Alvarez-Icaza R, Arthur JV, Merolla PA, Boahen K (2014) Neurogrid: A mixed-analog-digital multichip system for large-scale neural simulations. Proc IEEE 102(5):699–716

    Article  Google Scholar 

  7. Painkras E, Plana LA, Garside J, Temple S, Galluppi F, Patterson C, Lester DR, Brown AD, Furber SB (2013) Spinnaker: A 1-w 18-core system-on-chip for massively-parallel neural network simulation. IEEE J Solid-St Circ 48(8):1943–1953

    Article  Google Scholar 

  8. Akopyan F, Sawada J, Cassidy A, Alvarez-Icaza R, Arthur J, Merolla P, Imam N, Nakamura Y, Datta P, Nam GJ, Taba B, Beakes M, Brezzo B, Kuang JB, Manohar R, Risk WP, Jackson B, Modha DS (2015) Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip. IEEE Trans Comput Aided Des Integr Circuits Syst 34(10):1537–1557

    Article  Google Scholar 

  9. Sengupta  A, Roy K (2015) Spin-transfer torque magnetic neuron for low power neuromorphic computing. In Neural Networks (IJCNN), 2015 International Joint Conference on. IEEE, pp 1–7

  10. Park S, Sheri A, Kim J, Noh J, Jang J, Jeon M, Lee B, Lee B, Lee B, Hwang H (2013) Neuromorphic speech systems using advanced reram-based synapse. In Electron Devices Meeting (IEDM), 2013 IEEE International, pp 25–6

  11. Islam R, Li H, Chen P-Y, Wan W, Chen H-Y, Gao B, Wu H, Yu S, Saraswat K, Wong HP (2019) Device and materials requirements for neuromorphic computing. J Phys D Appl Phys 52(11):113001

    Article  Google Scholar 

  12. Ye Z, Liu R, Taggart JL, Barnaby HJ, Yu S (2018) Evaluation of radiation effects in rram-based neuromorphic computing system for inference. IEEE Trans Nucl Sci 66(1):97–103

    Article  Google Scholar 

  13. Yu S (2018) Neuro-inspired computing with emerging nonvolatile memorys. Proceedings of the IEEE 106(2):260–285

    Article  Google Scholar 

  14. Xia L, Li B, Tang T, Gu P, Chen P-Y, Yu S, Cao Y, Wang Y, Xie Y, Yang H (2017) Mnsim: Simulation platform for memristor-based neuromorphic computing system. IEEE Trans Comput Aided Des Integr Circuits Syst 37(5):1009–1022

    Google Scholar 

  15. Liu B, Yang C, Li H, Chen Y, Wu Q, Barnell M (2016) Security of neuromorphic systems: Challenges and solutions. In 2016 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, pp 1326–1329

  16. Hu M, Li H, Chen Y, Wu Q, Rose GS, Linderman RW (2014) Memristor crossbar-based neuromorphic computing system: A case study. IEEE transactions on neural networks and learning systems 25(10):1864–1878

    Article  Google Scholar 

  17. Liu C, Hu M, Strachan JP, Li H (2017) Rescuing memristor-based neuromorphic design with high defects. In 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC). IEEE, pp 1–6

  18. Liu X, Mao M, Liu B, Li B, Wang Y, Jiang H, Barnell M, Wu Q, Yang J, Li H et al (2016) Harmonica: A framework of heterogeneous computing systems with memristor-based neuromorphic computing accelerators. IEEE Trans Circuits Syst Regul Pap 63(5):617–628

    Article  Google Scholar 

  19. Greenlee JD, Shank JC, Tellekamp MB, Zhang EX, Bi J, Fleetwood DM, Alles ML, Schrimpf RD, Doolittle WA (2013) Radiation effects on linbo \(\_2\) memristors for neuromorphic computing applications. IEEE Trans Nucl Sci 60(6):4555–4562

    Article  Google Scholar 

  20. Naous R, Zidan MA, Sultan-Salem A, Salama KN (2014) Memristor based crossbar memory array sneak path estimation. In 2014 14th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA). IEEE, pp 1–2

  21. Cassuto Y, Kvatinsky S, Yaakobi E (2016) Information-theoretic sneak-path mitigation in memristor crossbar arrays. IEEE Trans Inf Theory 62(9):4801–4813

    Article  MathSciNet  Google Scholar 

  22. Hu M, Li H, Wu Q, Rose GS (2012) Hardware realization of bsb recall function using memristor crossbar arrays. In DAC Design Automation Conference 2012. IEEE, pp 498–503

  23. Zidan MA, Eltawil AM, Kurdahi F, Fahmy HA, Salama KN (2014) Memristor multiport readout: A closed-form solution for sneak paths. IEEE Trans Nanotechnol 13(2):274–282

    Article  Google Scholar 

  24. Kannan S, Karri R, Sinanoglu O (2013) Sneak path testing and fault modeling for multilevel memristor-based memories. In 2013 IEEE 31st International Conference on Computer Design (ICCD). IEEE, pp 215–220

  25. Huang L, Joseph AD, Nelson B, Rubinstein BI, Tygar JD (2011) Adversarial machine learning. In Proceedings of the 4th ACM Workshop on Security and Artificial Intelligence. ACM, pp 43–58

  26. Papernot N, McDaniel PD, Goodfellow IJ (2016) Transferability in machine learning: from phenomena to black-box attacks using adversarial samples. CoRR, abs/1605.07277

  27. Bagheri A, Simeone O Rajendran B (2018) Adversarial training for probabilistic spiking neural networks. In 19th IEEE International Workshop on Signal Processing Advances in Wireless Communications, SPAWC 2018, Kalamata, Greece, June 25-28, p 1–5

  28. Bhunia S, Hsiao MS, Banga M, Narasimhan S (2014) Hardware trojan attacks: threat analysis and countermeasures. Proc IEEE 102(8):1229–1247

    Article  Google Scholar 

  29. Tehranipoor M, Salmani H, Zhang X (2014) Hardware trojan detection: Untrusted third-party ip cores. In Integrated Circuit Authentication. Springer, pp 19–30

  30. Bostrom N (2017) Strategic implications of openness in ai development. Global Pol 8(2):135–148

    Article  Google Scholar 

  31. Hengstler M, Enkel E, Duelli S (2016) Applied artificial intelligence and trust @ tthe case of autonomous vehicles and medical assistance devices. Technol Forecast Soc Chang 105:105–120

    Article  Google Scholar 

  32. Burkitt AN (2006) A review of the integrate-and-fire neuron model: I homogeneous synaptic input. Biol Cybern 95(1):1–19

    Article  MathSciNet  Google Scholar 

  33. Orhan E (2012) The leaky integrate-and-fire neuron model. 3:1–6

    Google Scholar 

  34. Mihalaş Ş, Niebur E (2009) A generalized linear integrate-and-fire neural model produces diverse spiking behaviors. Neural Comput 21(3):704–718

    Article  MathSciNet  Google Scholar 

  35. Van Rossum MC, Bi GQ, Turrigiano GG (2000) Stable hebbian learning from spike timing-dependent plasticity. J Neurosci 20(23):8812–8821

    Article  Google Scholar 

  36. Prezioso M, Merrikh-Bayat F, Hoskins B, Adam GC, Likharev KK, Strukov DB (2014) Training and operation of an integrated neuromorphic network based on metal-oxide memristors. CoRR, abs/1412.0611

  37. Matveyev Y, Egorov K, Markeev A, Zenkevich A (2015) Resistive switching and synaptic properties of fully atomic layer deposition grown tin/hfo2/tin devices. J Appl Phys 117(4)

  38. Tan ZH, Yang R, Terabe K, Xue-Bing Y, Zhang XD, Guo X (2015) Synaptic metaplasticity realized in oxide memristive devices. Adv Mater (Deerfield Beach, Fla.), vol. 28, 11

  39. Iakymchuk T, Muñoz AR, Guerrero-Martínez J, Bataller-Mompeán M, Francés-Víllora JV (2015) Simplified spiking neural network architecture and STDP learning algorithm applied to image classification. EURASIP J. Image and Video Processing 2015:4

    Article  Google Scholar 

  40. Rovere G, Ning Q, Bartolozzi C, Indiveri G (2014) Ultra low leakage synaptic scaling circuits for implementing homeostatic plasticity in neuromorphic architectures. pp 2073–2076

  41. Fang H, Shrestha A, Ma D, Qiu Q (2018) Scalable noc-based neuromorphic hardware learning and inference. In 2018 International Joint Conference on Neural Networks, IJCNN 2018, Rio de Janeiro, Brazil. pp 1–8

  42. Luo Y, Wan L, Liu J, Harkin J, McDaid L, Cao Y, Ding X (2018) Low cost interconnected architecture for the hardware spiking neural networks. Front Neurosci 12:857

    Article  Google Scholar 

  43. Ancajas DM, Chakraborty K, Roy S. Fort-nocs: Mitigating the threat of a compromised noc. pp 1–6, 2014

  44. Shridevi RJ, Ancajas DM, Chakraborty K, Roy S (2015) Runtime detection of a bandwidth denial attack from a rogue network-on-chip. pp 8:1–8:8

  45. Zidan MA, Fahmy HAH, Hussain MM, Salama KN (2013) Memristor-based memory: The sneak paths problem and solutions. Microelectron J 44(2):176–183

    Article  Google Scholar 

  46. Querlioz D, Bichler O, Gamrat C (2011) Simulation of a memristor-based spiking neural network immune to device variations. In Neural Networks (IJCNN), The 2011 International Joint Conference on. IEEE, pp 1775–1781

  47. Yakopcic C, Taha TM, Subramanyam G, Pino RE (2013) Memristor spice model and crossbar simulation based on devices with nanosecond switching time. In Neural Networks (IJCNN), The 2013 International Joint Conference on, IEEE, pp 1–7.

  48. Boulet P, Devienne P, Falez P, Polito G, Shahsavari M, Tirilly P (2017) N2S3, an Open-Source Scalable Spiking Neuromorphic Hardware Simulator. PhD thesis, Université de Lille 1, Sciences et Technologies; CRIStAL UMR 9189

  49. Shahsavari M, Boulet P (2017) Parameter exploration to improve performance of memristor-based neuromorphic architectures. IEEE Transactions on Multi-Scale Computing Systems

  50. LeCun Y, Bottou L, Bengio Y, Haffner P (1998) Gradient-based learning applied to document recognition. Proc IEEE 86(11):2278–2324

    Article  Google Scholar 

  51. Deng L (2012) The mnist database of handwritten digit images for machine learning research [best of the web]. IEEE Signal Process Mag 29(6):141–142

    Article  Google Scholar 

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Acknowledgements

This work was supported in part by National Science Foundation grants (CNS-1117425, CAREER-1253024, CCF-1318826, CNS-1421022, CNS-1421068). Any opinions, findings and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the NSF.

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Correspondence to Chidhambaranathan Rajamanikkam.

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Rajamanikkam, C., JS, R., Roy, S. et al. Understanding Security Threats in Emerging Neuromorphic Computing Architecture. J Hardw Syst Secur 5, 45–57 (2021). https://doi.org/10.1007/s41635-021-00110-8

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  • DOI: https://doi.org/10.1007/s41635-021-00110-8

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