Fault-tolerant routing in unique-path multistage interconnection networks

doi:10.1016/0020-0190(89)90123-3

Information Processing Letters

Volume 31, Issue 4, 22 May 1989, Pages 197-201

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Abstract

A routing scheme is described for communication in a multiprocessor system employing a unique-path multistage interconnection network in the presence of faults in the network. The scheme avoids faulty elements by routing the message to an incorrect destination and then making an extra pass to route to the correct destination. It is capable of tolerating all single faults and many multiple faults in all except the first and last stages of the network. The routing scheme is useful for tolerating both permanent as well as intermittent faults in the network. It is transparent to the processors in the system which eliminates the need for elaborate reconfiguration protocols. The hardware overhead for implementing the scheme is very small and no time-penalty is paid in the fault-free case.

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Cited by (3)

Distributed routing in a fault-tolerant multistage interconnection network
1997, Information Processing Letters
A distributed routing scheme is presented for fault-tolerant communication in a multistage interconnection network. When faults occur, the scheme bypasses faulty switching elements by routing the message to an intermediate processor and then making the second pass to reach the final destination. It is simple to implement this scheme in hardware and the overhead is low. No time-penalty is paid when there are no faults in the network. We have evaluated the reliability improvement achieved by the routing algorithm, and the improvement is shown to be significant.
Fault-Tolerant Routing in MIN-Based Supercomputers
1994, Journal of Parallel and Distributed Computing
We study methods for routing data in supercomputers that use multistage interconnection networks (MINs), in the presence of faulty components in the network. These methods are applicable to multiprocessors such as IBM GF11 and RP3. These methods are based on the concept of dynamic full access (DFA), which refers to the ability of the network to route data from any processor in the system to any other processor in a finite number of passes through the network. We introduce a graph model called the DFA graph of a MIN and show how it can be used to determine the DFA capability of the MIN under a given set of network faults. When the faults in the network satisfy certain special properties, we present algorithms for routing
- •
  any arbitrary permutation in a faulty Benes network, and
- •
  any Omega permutation in a faulty Omega network.
These algorithms are simple and operate in a distributed fashion. These techniques allow a supercomputer to efficiently realize permutations of data needed in a parallel computing environment despite the presence of faults in the network.
Fault-tolerant routing in unique-path multistage omega network
1992, Information Processing Letters

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Information Processing Letters

Fault-tolerant routing in unique-path multistage interconnection networks

Abstract

A survey and comparison of fault-tolerant multistage interconnection networks

Computer

Performance-related dependability evaluation of supercomputer systems

Reliability simulation of multiprocessor systems

A survey of interconnection networks

Computer

Advanced parallel processing with supercomputer architectures

Proc. IEEE

Distributed routing in a fault-tolerant multistage interconnection network

Fault-Tolerant Routing in MIN-Based Supercomputers

Fault-tolerant routing in unique-path multistage omega network