The integrated display controller (IDC) for VLSI-design workstations

Abstract

A display controller to accelerate the updating of the frame buffer in raster displays is presented. The advantage of a frame buffer system is the ability to display pictures of any complexity, flicker free. The disadvantage is the great amount of pixel data, which must be updated, when the picture is changed. The Integrated Display Controller (IDC) described in this paper gets its name from the fact that both a pixel plane and a processor are integrated on a single chip. An internal logical unit, a shifter and special memory are provided to process complete rows and columns of pixels, or some part of them in parallel. All operations are performed in one bus cycle, which means that all the pixels addressed in the row or column are modified at the same time. Due to the special organization of the IDC, time consuming operations like block transfer or scrolling can be done significantly faster than in conventional systems. An experimental IDC with a lower screen resolution is developed to demonstrate the feasibility of the design. It is intended for use in VLSI-design workstations, where a great quantity of data has to be manipulated.