Design note
New design for an 82720-based colour graphics generator

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Abstract

A low-cost Multibus-compatible graphics generator has been designed for a resolution of 512 × 512 pixels with a 3-bit colour code per pixel. The heart of the system is an 82720 graphics display controller (GDC). Usual designs of colour graphics generators use three different memory planes, each containing information corresponding to one of the three primary colours of the cathode ray tube (CRT). However, this approach requires a large PCB area and a large number of memories and transceivers. Further, the design does not use the full speed of present-day dynamic RAMs, as the three planes are read in parallel during display. In the scheme presented in this paper, the memory is partitioned into segments, three of which store graphics information corresponding to three colours. The three segments are read sequentially within each GDC read cycle, using the full speed of the dynamic RAMs. Moreover, memory segmentation reduces the chip count and PCB area considerably. The system can produce a character display of 40 rows with 64 characters in each row, and can magnify any part of the display by a factor of up to 16.

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1

P Prabhakar Rao is a technical officer in the Department of Electrical Engineering at the Indian Institute of Technology, Madras, where he is involved in the development and maintenance of microprocessorbased systems. He received his bachelor's degree in electronics from Anna University, Madras. Currently he is working for an MS in electrical engineering. His fields of interest are three-dimensional television, computer-aided design and graphics systems.

2

S Srinivasan was educated at the University of Madras and at the Indian Institute of Technology, Madras. Until recently he served on the faculty of the Indian Institute of Technology. He is currently teaching at the California Polytechnic State University at San Luis Obispo, USA. During 1977-78, he visited the FRG as a DAAD Fellow. During 1983-85, he was a visiting professor at the University of California at Davis, USA. His current research interests are in the fields of digital image processing and microprocessor applications. He is a Fellow of the Institution of Electronics and Telecommunication Engineers (India).

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