Self-checking logic arrays

doi:10.1016/0141-9331(89)90066-5

Microprocessors and Microsystems

Volume 13, Issue 4, May 1989, Pages 281-290

https://doi.org/10.1016/0141-9331(89)90066-5 Get rights and content

Abstract

Self-checking blocks may be used to ensure concurrent error detection in integrated circuits. On the other hand, logic arrays such as PLAs, ROMs and RAMs are essential to circumvent the increasing complexity of VLSI circuits. Efficient self-checking schemes for logic arrays are therefore essential for concurrent error detection in VLSI circuits. The paper describes schemes that incur low area overhead.

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Cited by (6)

Concurrent checking for VLSI
1999, Microelectronic Engineering
This paper presents various concurrent checking techniques for VLSI, including self-checking circuits and concurent checking techniques for temporary faults based on time redundancy. It cautions that emerging technological constraints and application requirements will expend dramatically the use of these techniques. In particular, various industrial sectors (e.g. railway control, satellites, avionics, telecommunications, control of critical automotive functions, medical electronics, industrial control, etc), have increasing needs for concurrent checking features. Some of these applications concern mass production and should support the standardization of such techniques and the development of commercial CAD tools supporting them. Furthermore, drastic device shrinking and increasing operating speeds that accompany the technological evolution to deeper submicron, reduces significantly the noise margins and increases dramatically the impact of transient faults. In addition various spurious faults are becoming predominant and require very complex test conditions. Under such conditions, test pattern generation complexity and test length make impossible the detection of such faults. As a consequence, technological progress will be blocked quickly if no particular actions are undertaken to cope with increasingly high soft-error rates and undetected spurious faults resulting on timing errors.
The paper will discuss these emerging requirements and problems and describe how concurrent checking can be used to cope with.
Design of minimal-level PLA self-testing checkers for m-out-of-n codes
1996, IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design techniques for soft-error mitigation
2010, 2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010
General design principles of totally self-checking code-disjoint inverter-free PLAs
2004, IEE Proceedings: Circuits, Devices and Systems
On-line testing for VLSI - A compendium of approaches
1998, Journal of Electronic Testing: Theory and Applications (JETTA)
General design principles of self-testing code-disjoint PLAs
1993, Proceedings of the Asian Test Symposium

^☆: This work has been supported by the EEC (Project No 888 AIDA)

^a: Michael Nicolaidis received an engineering doctorate from degree from the Polytechnic of Thessaloniki, Greece and an engineering doctorate from the Polytechnic Institute of Grenoble, France. Presently he is a researcher with CNRS, working at the TIM3/IMAG Laboratory in Grenoble. His research interests include fault-modelling, fault-tolerant computing, self-checking systems, design for testability, and CAD tools.

^b: Bernard Courtois received an engineering degree from the École Nationale Supéreure d'Informatique Appliquées de Grenoble, France in 1973 and engineering and science doctorates in 1973 from the Institut National Polytechnique de Grenoble, France. Since 1973, he has been researching fault tolerance, fault modelling and VLSI testing. He is currently responsible for the Computer Architecture Group of the IMaG/TIM3 Laboratory, where research interests include CAD, architecture, and VLSI testing.

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Self-checking logic arrays☆

Abstract

Design of dynamically checked computers

Design of self-checking digital networks using coding techniques

Strongly fault-secure logic networks

IEEE Trans. on Computers

Sequentially self-checking circuits

Strongly code disjoint checkers

IEEE Trans. on Computers

Failure mechanisms, fault hypotheses, and analytical testing of LSI-NMOS (HMOS) circuits

Layout rules for the design of self-checking circuit

Design of selfchecking circuits using unidirectional error detecting codes

The design of PLAs with concurrent error detection

Error detecting codes, self-checking circuits and applications

Efficient concurrent error detection in PLAs and ROMs