Systolic array implementation of artificial neural networks

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Abstract

This paper describes systolic implementation schemes for Hopfield and Hamming nets using completely digital circuits. In the proposed architecture, input data are passed through the neurons on a time share basis, weights are stored in digital shift registers and no separate threshold detectors are used. The architecture provides massive parallelism, reprogrammability and can be expanded by cascading identical chips.

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Cited by (0)

1

K Vijayan Asari received a BSc Engg degree in electronics and communications engineering from the University of Kerala, India in 1978 and an MTech degree in electrical engineering from the Indian Institute of Technology, Madras in 1984. He is currently working towards a PhD degree in the Department of Electrical Engineering, IIT, Madras. Since October 1984 he has been an assistant professor in the Department of Electronics and Communications Engineering, TKM College of Engineering, Quilon, India. His research interests are neural networks, multiple-valued logic, VLSI architectures and algorithms and signal processing.

2

Dr C Eswaran received his MTech and PhD degrees in electrical engineering from the Indian Institute of Technology, Madras, India. He is currently working as a professor in the Department of Electrical Engineering, Indian Institute of Technology, Madras. He has served as a visiting faculty member at Ruhr University, Bochum, Germany, Concordia University, Montreal, Canada. His research interests are in the areas of digital systems, microprocessors, digital signal processing and neural networks.

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