Systolic array implementation of artificial neural networks
References (21)
- et al.
An algebra for systolic computation
- et al.
- et al.
Connectionist architectures for artificial intelligence
IEEE Comput. Mag.
(1987) - et al.
- et al.
Implementing neural networks on parallel computers
Comput. J.
(1987) - et al.
VLSI implementation of a neural network model
Comput.
(March 1988) - et al.
The design of special purpose VLSI chips
Comput.
(January 1980) Let's design algorithms for VLSI systems
VLSI array processors
IEEE ASSP Mag.
(July 1985)An algorithm basis for systolic/wavefront array software
Cited by (0)
- 1
K Vijayan Asari received a BSc Engg degree in electronics and communications engineering from the University of Kerala, India in 1978 and an MTech degree in electrical engineering from the Indian Institute of Technology, Madras in 1984. He is currently working towards a PhD degree in the Department of Electrical Engineering, IIT, Madras. Since October 1984 he has been an assistant professor in the Department of Electronics and Communications Engineering, TKM College of Engineering, Quilon, India. His research interests are neural networks, multiple-valued logic, VLSI architectures and algorithms and signal processing.
- 2
Dr C Eswaran received his MTech and PhD degrees in electrical engineering from the Indian Institute of Technology, Madras, India. He is currently working as a professor in the Department of Electrical Engineering, Indian Institute of Technology, Madras. He has served as a visiting faculty member at Ruhr University, Bochum, Germany, Concordia University, Montreal, Canada. His research interests are in the areas of digital systems, microprocessors, digital signal processing and neural networks.