Performance analysis of Clos interconnection networks under non-uniform traffic patterns

doi:10.1016/0141-9331(96)01090-3

Microprocessors and Microsystems

Volume 20, Issue 5, September 1996, Pages 261-265

https://doi.org/10.1016/0141-9331(96)01090-3 Get rights and content

Abstract

In this paper we consider the performance behaviour of a multiprocessor system that employs Clos interconnection network under non-uniform traffic patterns. The study is based on the evaluation of the bandwidth of the system with the help of the hierarchical requesting model.

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Cited by (1)

Analytical simulation of multiprocessor architectures under non-uniform traffic loads
2000, Mathematics and Computers in Simulation
The performance analysis of network architecture is a very crucial factor in designing multiprocessor systems. Very often, simulation is the only feasible method because of the nature of the problem and because analytical techniques become too difficult to handle. However, simulation can be costly to develop and run. The mathematical analysis approach is preferable but in most cases not applicable. This paper presents an analytical simulation method that can be used for the evaluation of interconnection network architectures that are based on buffered banyan networks. This method comprises the probabilistic analysis and the simulation technique with the help of a mathematical software package MathConnex (of MathSoft Corporation). The analysis enables us to observe the behavior of various stages of the network architecture under various traffic conditions.

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Microprocessors and Microsystems

Performance analysis of Clos interconnection networks under non-uniform traffic patterns

Abstract

An analysis of processor-memory interconnection networks

IEEE Trans. Comput.

Performance analysis of multiple bus interconnection networks with hierarchical requesting model

IEEE Trans. Comput.

Performance analysis of multistage interconnection networks with hierarchical requesting model

IEEE Trans. Comput.

A survey of interconnection networks

IEEE Comput.

Performance of processor-memory interconnections for multiprocessors

IEEE Trans. Compt.

Tutorial: Interconnection networks for parallel and distributed processing

IEEE Computer Society

Analytical simulation of multiprocessor architectures under non-uniform traffic loads