Performance analysis of distributed memory computers with parallel node architecture

Abstract

In a distributed memory computer (DMC), parallelism at node level can be achieved by use of pipelined arithmetic units or communication processors that allow overlap between processing and communication activities. We derive a performance model for distributed memory computers whose nodes are vector-processing elements (VPEs), i.e., nodes with a parallel internal architecture. The model is based on the one introduced by Hockney for SIMD computers and shared-memory MIMD architectures. The approach has been extended to distributed-memory architectures, including VPE networks, to achieve a powerful characterization of these systems in terms of a few performance parameters. The discussion points out how vector capabilities can be effectively exploited in DMCs and identifies the parameters of the concurrent system (hardware and software) that most significantly affect the overall performance. Finally, the generality of the model is discussed with respect to different kinds of VPE architectures proposed in the literature or available on the market.