Partitioning of digital designs: a knowledge based approach and concepts for its parallelization

Abstract

Partitioning of digital circuits is an essential task in logical circuit design. Whenever the total circuit doesn't fit onto one physical unit (circuit board, VLSI Chip), it must be distributed to several units in a way appropriate for the technology used. The number of units should be small. In the case of gate arrays the admissable number of gates and pins must not be exceeded. After partitioning performance requirements must be met.

The number of possible partitionings grows more than exponentially with the size of a design, that even small and medium size circuits cannot be evaluated in an acceptable amount of time. The designer uses heuristics to select appropriate steps for partitioning. He rates them and tracks the most promising way. This decision later may turn out to be wrong, forcing the designer to return to another intermediate state as starting point for a new attempt.

To solve this problem the expert system Chipex (Chip-Expert) was developed. Chipex imitates the designer's procedure by evaluating a decision tree. To achieve further speedup of the system different approaches of parallelization are investigated.