Scheduliing expression trees with register variables on delayed-load architectures

doi:10.1016/0165-6074(94)90102-3

Microprocessing and Microprogramming

Volume 40, Issue 8, October 1994, Pages 577-596

Microprocessing and ...

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Abstract

In this paper, we describe an optimal, linear time instruction scheduling algorithm for scheduling expression trees on delayed-load architectures with unit latency times. The algorithm is a generalization of the algorithm due to Proebsting and Fischer and handles expression trees with register variables. Register variables are useful in code generation across basic block boundaries and in code generation from DAGs. Register allocation is integrated with instruction scheduling. Spilling is handled optimally. The algorithm acts as a good heuristic for longer latency times and in code generation from DAGs.

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Cited by (1)

Scheduling expression trees for delayed-load architectures
2002, Journal of Systems Architecture
Citation Excerpt :
Thus, an algorithm which handles register variables can avoid these stores and loads at the shared nodes of the DAG. Ref. [10] considers the problem in which one or more of the leaves of the tree contain values already loaded into registers. However, there is still the restriction that these registers are not used further in the evaluation of the tree.
In this paper we consider the problem of scheduling expression trees on delayed-load architectures. The problem tackled here takes root from the one considered in [Proceedings of the ACM SIGPLAN ’91 Conf. on Programming Language Design and Implementation, 1991. p. 256] in which the leaves of the expression trees all refer to memory locations. A generalization of this involves the situation in which the trees may contain register variables, with the registers being used only at the leaves. Solutions to this generalization are given in [ACM Trans. Prog. Lang. Syst. 17 (1995) 740, Microproc. Microprog. 40 (1994) 577]. This paper considers the most general case in which the registers are reusable. This problem is tackled in [Comput. Lang. 21 (1995) 49] which gives an approximate solution to the problem under certain assumptions about the contiguity of the evaluation order. Here we propose an optimal solution (which may involve even a non-contiguous evaluation of the tree). The schedule generated by the algorithm given in this paper is optimal in the sense that it is an interlock-free schedule which uses the minimum number of registers required. An extension to the algorithm incorporates spilling. The problem as stated in this paper is an instruction scheduling problem. However, the problem could also be rephrased as an operations research problem with a difference in terminology.

¹: R. Venugopal obtained his B. Tech. and MSc (Engg.) degrees in 1989 and 1992 respectively, both in Computer Science. Presently he is working towards his Ph.D. in Computer Science at the Indian Institute of Science, Bangalore. His areas of interest are compilers and computer architecture.

²: Y.N. Srikant received his Ph.D. in Computer Science from the Indian Institute of Science in 1986 where he is currently an Associate Professor. His current research interests are in the areas of parallelization, code generation, incremental compilation and parallel compilation. He has published more than 30 research papers in the area of compilers. He was awarded the Young Scientist medal in 1988 by the Indian National Science Academy for his work in compilers.

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Scheduliing expression trees with register variables on delayed-load architectures

Abstract

Code generation for expressions with common subexpressions

J. ACM

Compilers: Principles, Techniques and Tools

Scheduling arithmetic and load operations in parallel with no spilling

SIAM J. Comput.

Computers and Intractability A Guide to the Theory of NP-Completeness

Efficient instruction scheduling for a pipelined architecture

Parallel sequencing and assembly line problems

Opera. Res.