Microprocessing and Microprogramming
Scheduliing expression trees with register variables on delayed-load architectures
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Cited by (1)
Scheduling expression trees for delayed-load architectures
2002, Journal of Systems ArchitectureCitation Excerpt :Thus, an algorithm which handles register variables can avoid these stores and loads at the shared nodes of the DAG. Ref. [10] considers the problem in which one or more of the leaves of the tree contain values already loaded into registers. However, there is still the restriction that these registers are not used further in the evaluation of the tree.
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R. Venugopal obtained his B. Tech. and MSc (Engg.) degrees in 1989 and 1992 respectively, both in Computer Science. Presently he is working towards his Ph.D. in Computer Science at the Indian Institute of Science, Bangalore. His areas of interest are compilers and computer architecture.
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Y.N. Srikant received his Ph.D. in Computer Science from the Indian Institute of Science in 1986 where he is currently an Associate Professor. His current research interests are in the areas of parallelization, code generation, incremental compilation and parallel compilation. He has published more than 30 research papers in the area of compilers. He was awarded the Young Scientist medal in 1988 by the Indian National Science Academy for his work in compilers.