A VLSI systolic architecture for solving DBT-transformed fuzzy clustering problems of arbitrary size

Abstract

This article presents a VLSI systolic architecture for solving fuzzy C-means clustering problems of arbitrary size with an array of fixed size. The array design assumes that the data fed in have been subjected to the DBT transformation (dense-to-band matrix transformation by triangular block partitioning). The architectural configuration of the various subarrays involved are presented together with the internal structure of their processing elements, and the performance is analysed. The modularity and regularity of the design make it highly suitable for VLSI implementation.