Mapping uniform loop nests onto distributed memory architectures
References (21)
Regular partitioning for synthesizing fixed-size systolic arrays, INTEGRATION
The VLSI J.
(Dec. 1991)- et al.
The data alignment phase in compiling programs for distributed memory machines
J. Parallel Distributed Comput.
(1991) - et al.
A design methodology for fixed-size systolic arrays
An introduction to a formal theory of dependence analysis
J. Supercomput.
(1988)- et al.
Loop nest scheduling and transformations
- et al.
Affine-by-statement scheduling of uniform loop nests over parametric domains
Dataflow analysis of array and scalar references
Internat. J. Parallel Programming
(1991)- et al.
Graphs and Algorithms
(1984) - et al.
Compiler optimizations for Fortran D on MIMD distributed-memory machines
There are more references available in the full text version of this article.
Cited by (24)
Optimal Scheduling for UET/UET-UCT Generalizedn-Dimensional Grid Task Graphs
1999, Journal of Parallel and Distributed ComputingMapping affine loop nests
1996, Parallel ComputingCompiling affine nested loops: How to optimize the residual communications after the alignment phase
1996, Journal of Parallel and Distributed ComputingCompiling for massively parallel architectures: a perspective
1995, Microprocessing and MicroprogrammingMulti-objective processor-set selection for computational cluster-systems
2013, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)Control generation for QR decomposition based on the polytope model
2009, 2009 6th International Conference on Electrical Engineering, Computing Science and Automatic Control, CCE 2009
- †
Supported by the Project C3 of the French Council for Research CNRS, and by the ESPRIT Basic Research Action 6632 ‘NANA2’ of the European Economic Community.
Copyright © 1994 Published by Elsevier B.V.