Elsevier

Parallel Computing

Volume 20, Issue 5, May 1994, Pages 679-710
Parallel Computing

Mapping uniform loop nests onto distributed memory architectures

https://doi.org/10.1016/0167-8191(94)90001-9Get rights and content

Abstract

This paper deals with scheduling, mapping and partitioning techniques for uniform loop nests. Target machines are SPMD distributed memory parallel computers. We use affine-by-statement scheduling and affine-by-variable mapping to synthesize a virtual grid architecture from the original loop nest. The virtual grid architecture is then partitioned into a physical processor grid. The key to the mapping strategy is the communication graph, which enables us to derive optimal mappings, i.e. where the number of communications is proved to be minimal. The partitioning technique extends the methods developed for systolic array design methodologies to loop nests with several statements.

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Supported by the Project C3 of the French Council for Research CNRS, and by the ESPRIT Basic Research Action 6632 ‘NANA2’ of the European Economic Community.

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