Elsevier

Integration

Volume 12, Issue 2, December 1991, Pages 211-235
Integration

A flexible hierarchical piecewise linear simulator

https://doi.org/10.1016/0167-9260(91)90036-KGet rights and content

Abstract

In this paper, a piecewise linear (PL) simulator, called PLANET, will be presented. New features in contrast to other existing (piecewise linear) simulators are a flexible hierarchical data structure which retains the hierarchy in the simulated system, and the use of a simplified form of the Katzenelson algorithm to solve the circuit equations. Owing to the PL-concept, the simulator is capable of performing full mixed-level and mixed-mode simulations. Due to the new concept, the hierarchically organized simulator can be used by advantage in a hierarchical design environment. The replacement of a single component by a subcircuit becomes facile. The hierarchical representation of a circuit or system makes it easy to exploit latency in a circuit by means of numerical integration techniques having variable stepsize or by employing an event-driven approach.

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Cited by (8)

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1

T.A.M. Kevenaar was born in Tilburg. The Netherlands, on August 14, 1961. He received the Ir. degree in electrical engineering in 1986 from the Eindhoven University of Technology, Eindhoven. After his military service he joined Philips labs for a projcet on a compact switchmode power supply. In 1989 he joined the Electronic design group of the Eindhoven University of Technology as a PhD student. His interests are in the field of circuit simulation, timing verification and atuomation of analog design.

2

D.M.W. Leenaerts was born in Geldrop, The Netherlands, on January 2, 1964. He received the Ir. degree in electrical engineering in 1987 from the Eindhoven University of Technology, Einhoven, The Netherlands. In the same year he joined the Electronic design group, Eindhoven University of Technology where he is currently working towards his PhD degree in electronics. His research interests are in design of analog integrated circuits, nonlinear system analysis and synthesis and in analog design automation (synthesis and analysis).

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