Article
Lockup-free caches in high-performance multiprocessors

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Abstract

The performance of shared-memory multiprocessors can suffer greatly from moderate cache miss rates because of the usually high ratio between memory access and cache access times. In this paper we propose a cache design in which the handling of one or several cache misses occurs concurrently with processor activity. Concurrent miss resolution in multiprocessor caches must function in conjunction with the system's synchronization hardware and cache coherence protocol. Through performance models, we identify system configurations for which concurrent miss resolution is effective. Compiler techniques to take advantage of the proposed design are illustrated at the end of the paper.

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This research is supported by NSF Research Grant CCR-8709997.

Current address: Intel Corporation, 2625 Walsh Ave., Santa Clara, CA 95051.

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