ArticleLockup-free caches in high-performance multiprocessors☆
References (19)
Cache memories
ACM Comput. Surveys
(Sept. 1982)Using cache memory to reduce processor-memory traffic
- et al.
A new solution to coherence problems in multicache systems
IEEE Trans. Comput.
(Dec. 1978) Lockup-free instruction fetch/prefetch cache organization
- et al.
SIMP (single instruction stream/multiple instruction pipelining): A novel high-speed single-processor architecture
The IBM research parallel processor prototype (RP3 ): Introduction and architecture
- et al.
RP3 processor-memory element
How to make a multiprocessor computer that correctly executes multiprocess programs
IEEE Trans. Comput.
(Sept. 1979)- et al.
Memory access dependencies in shared memory multiprocessors
IEEE Trans. Software Eng.
(June 1990)
There are more references available in the full text version of this article.
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This research is supported by NSF Research Grant CCR-8709997.
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