Regular articleSYNAPSE—A neurocomputer that synthesizes neural algorithms on a parallel systolic engine
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RRAM/memristor for computing
2019, Advances in Non-volatile Memory and Storage Technology, Second EditionDigital implementation of a virtual insect trained by spike-timing dependent plasticity
2016, Integration, the VLSI JournalCitation Excerpt :Even with these advantages, hardware implementations are still sought after because of the speed associated with hardware computing; realization of adequate neural processors or neurocomputers will enable applications that require real-time processing, feedback, and learning. The most promising implementations use the digital components and have granted programmable neurocomputers like CNAPS [9] and SYNAPSE-1 [10]. Although neurocomputers are very powerful, efforts have been made to scale down applications to even less powerful machines, ones that run on battery and do not rely on a large number of processing elements.
Scalable network-on-chip architecture for configurable neural networks
2011, Microprocessors and MicrosystemsCitation Excerpt :Hence, they are less suitable for general purpose neural network chips. Systolic array implementations of NN, such as SYNAPSE [36] imply a fixed interconnect topology and are limited in the models that they can implement. Systolic arrays are most suitable to conventional static neural networks (compute-bounded problem), but inadequate for the simulation of spiking neural networks (interconnect-bounded problem).
PARNEU: general-purpose partial tree computer
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