Complexity theory of parallel time and hardware☆

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Abstract

The parallel resources time and hardware and the complexity classes defined by them are studied using the aggregate model. The equivalence of complexity classes defined by sequential space and uniform aggregate hardware is established. Aggregate time is related to (bounded fanin) circuit depth and, similarly, aggregate hardware is related to circuit width. Interelationships between aggregate time and hardware follow as corollaries. Aggregate time is related to the sequential resource reversal. Simultaneous relationships from aggregate hardware and time to sequential space and reversal are shown (and conversely), and these are used as evidence for an “extended parallel computation thesis.” These simultaneous relationships provide new characterizations for the simultaneous parallel complexity class NC and for the complementary class SC. The evaluation of monotone planar circuits is shown to be in NC, in fact in LOGCFL.

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This paper is based on the first author's Ph.D. thesis. A preliminary version of this paper appeared as (Dymond and Cook, 1980). This research was supported in part by the Natural Sciences and Engineering Research Council of Canada, and by the National Science Foundation under Contract DCR-8604031.

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Current address: Department of Computer Science and Engineering, Mail Code C-014, University of California, San Diego, La Jolla, CA 92093.

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