Thin-film silicon-on-sapphire LDMOS structures for RF power amplifier applications

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Abstract

This work is addressed to the investigation of the electro-thermal performance of RF-LDMOS transistors integrated in TF-SOI, TF-SOS and thinned TF-SOS substrates by means of numerical simulations. Reported experimental trap density, carrier mobility and capture cross-section values have been used together with sapphire datasheet thermal properties, in order to provide accurate simulation results. It is found that subthreshold characteristics are the same for all the analysed substrates while blocking-state, on-state and power dissipation process depends on the substrate type.

Introduction

Recent advances and new requirements on wireless communications have favoured the research on RF circuits integrated on Silicon-On-Sapphire (SOS) substrates using CMOS technology [1], and the development of power amplifiers on Silicon-On-Insulator (SOI) substrates including LDMOS devices to provide voltage capability up to 30 V [2]. These challenges have also been possible due to the improvement of the Thin Film SOI and SOS (TF-SOI and TF-SOS) substrates manufacturing technologies, leading to high quality active silicon layers. Up to now, LDMOS devices for RF applications are not integrated on SOS substrates because of the low carrier mobility, the high leakage current levels caused by the large trap density [3] and the manufacturing cost of high quality substrates.

Advantages of SOI technology vs. bulk technology in the RF application field have been largely reported [4]. The difficulty to combine high-frequency power transistors with high Q on-chip inductors lead to bulk RF amplifiers implemented on standard CMOS technologies with a relatively low level of integration. RF power amplifiers integrated on SOI technology have been recently developed in order to improve the high-frequency performance and to eliminate the cross-talk and latch-up phenomena. Moreover, on-chip inductors with a relatively high Q factor can be easily achieved on SOI technology with a low P-type substrate doping concentration and a thick buried oxide. Furthermore, the SOI technology provides better immunity to radiation induced ionisation currents, thus reducing the soft errors in CMOS systems and circuits.

In order to fit the electrical performances of SOI RF power amplifiers to the requirements of the new telecommunication standards, a significant effort has been recently devoted to the improvement of SOI LDMOS structures [2], [5], [6].

On the other hand, CMOS ICs integrated on SOS substrates show several advantages with respect to CMOS ICs integrated on SOI technology.

  • •

    High Q factor inductors, due to the reduction of substrate losses.

  • •

    Better heat extraction capability from the active silicon layer in dynamic and stationary operation modes since the sapphire thermal conductivity is higher than that of the buried oxide.

  • •

    Reduction of the parasitic bipolar gain, leading to a smaller current kink magnitude and a higher kink onset voltage.

  • •

    Reduction of the impact ionisation process, thus increasing the breakdown voltage.

The crystallographic quality of the active silicon layer on TF-SOS substrates has been largely improved in the last decade [7], [8], [9], [10], [11]. Hence, LDMOS structures for RF power amplifiers seem to be feasible since the leakage current levels can be significantly reduced and carrier mobility enhanced. An LDMOS transistor integrated on SOS substrates was reported on 1997 [12], the linearity required for RF applications being demonstrated.

This paper reports for the first time a detailed study of the electro-thermal performance of LDMOS transistors integrated on SOS substrates based on numerical simulations. The reported data on high level trap concentration, low mobility, capture cross-section and sapphire thermal skills have been included in the performed simulations.

Section snippets

Electro-thermal simulations

Electro-thermal simulations have been carried out with DESSIS software [13] to compare the electrical performance of SOS and SOI LDMOS equivalent structures. The cross-sectional view of an SOS LDMOS structure is shown in Fig. 1. The geometrical and technological parameters have been chosen according to the fabricated SOI LDMOS transistors [14] for RF applications. The physical values listed in Table 1 have been introduced into the mobility, recombination and trap models used to perform

Blocking state mode

Variation on the breakdown voltage (Vbr) values in TF-SOI and TF-SOS LDMOS have been found in the performed electro-thermal simulations. As inferred from Fig. 2, simulated Vbr values are 18 and 23 V in TF-SOS and TF-SOI LDMOS transistors, respectively. Breakdown in LDMOS transistors is a consequence of the parasitic bipolar activation. Simulated Vbr values of similar TF-SOI and TF-SOS diode structures are higher (40 V) than LDMOS counterparts since no parasitic bipolar structure is present and

Power dissipation process

Additional thermal one-dimensional simulations have been carried out with DESSIS software to analyse the self-heating process of the active silicon region on TF-SOI, TF-SOS and thinned TF-SOS substrates.

The heat generation is emulated by a constant superficial power dissipation pulses per unit area (P) and the thermal resistance and capacitance of the active silicon region is neglected in the performed simulations. The thermal effect of this layer has to be taken into account at higher

Conclusions

Performed simulations have shown that LDMOS transistors integrated in TF-SOS substrates exhibit better electro-thermal performances respect to TF-SOI counterparts. A reduction of floating body effect and an increase of the breakdown voltage by optimising the LDMOS transistor has been observed. Despite these advantages, a reduction of the SOA in TF-SOS LDMOS transistors has been found due to the lower carrier mobility and the larger substrate thermal resistance. This problem can be solved by

Acknowledgements

This work was supported by the Comisión Interministerial de Ciencia y Tecnologı́a (CICYT) (ref. TIC2002-02564).

References (21)

  • N. Hefyene et al.

    Adaptation of the pseudo-MOS transistor for the characterization of SOS films

    Solid State Electron.

    (2000)
  • J. Pretet et al.

    Electrical evaluation of innovating processes for improving SOS materials

    Microelectron. Engng

    (2001)
  • J. Roig et al.

    Analysis of breakdown voltage in SOI and SOS technologies

    Solid State Electron.

    (2002)
  • R.A. Johnson et al.

    Advanced thin-film silicon-on-sapphire technology: microwave circuit applications

    IEEE Trans. Electron. Devices

    (1998)
  • J.G. Fiorenza et al.

    RF Power LDMOSFET on SOI

    IEEE Electron. Device Lett.

    (2001)
  • N. Jiping et al.

    JFET/SOS devices: processing and gamma radiation effects

    (1998)
  • L.E. Larson

    Integrated circuit technology options for RFIC's—present status and future directions

    IEEE J. Solid State Circuits

    (1998)
  • P. Khandelwal et al.

    Thermal and package performance limitations in LDMOSFET's for RFIC applications

    IEEE Trans. Microwave Th. and Tech.

    (1999)
  • M. Kumar et al.

    An SOI LDMOS/CMOS/BJT technologies for integrated power amplifiers used in wireless tranceiver applications

    IEEE Trans. Electron. Devices

    (2001)
  • G.A. Garcia et al.

    High-quality CMOS in thin (100 nm) silicon on sapphire

    IEEE Trans. Electron. Devices

    (1988)
There are more references available in the full text version of this article.

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