Correlation between predicted cause of SRAM failures and in-line defect data

Abstract

A correlation has been made between the bitmap data from an SRAM and the in-line defect data as measured on a KLA2122 and Tencor7700. The SRAM was a dedicated design for yield enhancement in a 0.35 μm technology. Extra design features were added to encourage the change of having defect on particular places and discourage it on safe designed places. From the failure signature of a memory cell (0 or 1) and its failure extent (single cell, double cell, bitline, wordline (WL), …) one can predict the process-related cause of the failure. A special test program has been written which translates the electrical data from the failing cells into its process defect.

The failing bits from the SRAM have been transferred into a KLA results file and added as an extra inspection to the defect database. With a defect source analysis it was possible to find out if the electrical failing bits were seen as a defect in the line and at which steps. With this analysis it is possible to find out if the predicted cause of the process defects from the test program is confirmed by the performed in-line inspections. With an intensive inspection plan about half of the electrical defects were seen in the line. For a large amount of these defects their predicted cause are indeed matching with the inspected layer. Moreover, quite some unknown failures can be explained by the in-line inspections. This correlation work makes it possible to prioritize in tackling the most killing defect sources.

Introduction

A static RAM is widely used as a process monitor [1], [2], [3], [4], [5], [6], [7]. Its full process topology, its efficient use of silicon area, its similar topology and failure rate as normal logic circuits and its relative ease of defect localization, determine the success of an SRAM as test vehicle.

However one can easily locate a failing cell in an SRAM, the failure location within the cell is not found immediately. The ignorance of the exact location within the cell makes failure analysis still a time consuming job and slows down the learning rate for yield improvement. To limit the amount of failure analysis and to be able to predict the process-related defect, people started to perform defect simulations. This lead to the generation of so-called defect-bitmap dictionaries containing about a million kinds of process defects, their likelihood to occur and their related bitmaps [3], [4], [5], [6], [7]. These dictionaries do not provide unique defect types for each possible bitmap, but quite often different types were possible or even unknown types. Extra IDDQ testing is sometimes used to improve the distinction between the possible defect types [3], [7].

For this work a dedicated SRAM has been developed with extra critical design features to enhance the chance of having killing defects at certain process levels. This SRAM is used as a yield improvement test vehicle for a 0.35 μm CMOS technology [8]. A new test program and accessory test vehicle has been developed which make it possible to determine the failing part of the cell in a time period of only about a tenth of a millisecond and, thanks to the dedicated design, the failing design feature in the cell [9]. Simple de-processing or X-section using focussed ion beam through this design feature reveals the exact process defect. The real cause of the process defect has of course still to be determined, but this technique drives the process development and support engineers immediately and unambiguously in the right direction for yield improvement.