Introductory Invited paper
Progress in device isolation technology

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Abstract

This contribution gives a brief overview on the current status of device isolation technology. Starting with conventional shallow-trench-isolation (STI), the challenges introduced by this approach are outlined. Based on this discussion, the concept of the recently developed extended trench isolation gate technology (EXTIGATE) is presented. It will be shown that EXTIGATE not only provides a relief from the drawbacks of conventional STI processing, but also offers promising alternatives for front-end process integration, device optimization and specific applications.

Introduction

Without device isolation technology, the realization of integrated circuits as we know today, like processors, dynamic or non-volatile memories and system-on-chip applications would not have been possible. For several decades, local oxidation of silicon (LOCOS) [1] was the ultimate isolation technique used in MOS and bipolar technologies to ensure undisturbed operation of thousands of integrated active devices. However, as technologies were approaching the 0.25 μm design rule, the limitations of LOCOS isolation became more and more apparent. Besides the substantial lateral active-area loss due to field oxide encroachment, the non-planarity between isolation oxide and active area also caused increased difficulties for lithography and etching. In order to overcome this bottleneck, shallow-trench-isolation (STI) [2], [3] was introduced. STI is scalable to extremely high packing densities because of the abrupt transition between active device and isolation regions and it provides the desired planar surface topology. However, these advantages come not for free. STI processing is much more complex than previous LOCOS technology and demands for a much tighter process control. Besides being more expensive, STI adversely affects device characteristics. In particular the enhanced sub-threshold leakage (parasitic corner effect) [4] and the narrow width effect [5] are among the major drawbacks. Moreover, the perimeter component will become more important in future technology generations since the area-to-perimeter ratio tends to decrease in further downscaled devices.

This contribution briefly reviews the current status on device isolation technology. Starting with conventional STI, the challenges introduced by this approach are outlined. Based on this discussion, the process concept of the recently developed extended trench isolation gate technology (EXTIGATE) [6], [7], [8], [9], [10], [11], [12], [13] is presented. It will be shown that EXTIGATE not only provides a relief from the drawbacks of conventional STI but also offers promising alternatives for front-end process integration, device optimization and specific applications as well.

Section snippets

Challenges of conventional STI-CMOS

Conventional STI suffers from problems inherently related to the abrupt transition between active device and isolation regions, namely the trench corner. Since CMOS processing starts with the definition of active area and isolation regions, subsequent cleaning and etching sequences prior to gate oxidation often create under cuts in the isolation oxide which cause gate-wrap-around [4] (Fig. 1, left inset). In combination with oxide thinning and dopant loss at the side wall, the crowding of gate

Process concept

The EXTIGATE structure [6], [7], [8], [9], [10], [11], [12], [13] basically results from the fact that the essential part of the MOS gate is fabricated prior to device isolation on the bare wafer, as shown in Fig. 3. After wafer clean, the process starts with gate oxidation followed by bottom poly-Si and nitride deposition. For ultra-thin oxides this first step is favorably done by in situ cluster tool processing [11], [12], as discussed in Section 3.7. Subsequently, isolation and active-device

Conclusion

Device isolation technology has substantially advanced during the past years. Besides ensuring undisturbed operation of millions of integrated devices, device isolation is now becoming increasingly an active part in device optimization, process integration and in specific applications. For example, using innovative concepts like EXTIGATE, ultra-dense DRAM and flash memories have been realized. We therefore conclude, that device isolation technology will further gain importance in the

Acknowledgements

The author would like to thank Dr. Preussger and Meinhard Obry for their encouragement, Dr. Kerber, Dr. Pompl, M. Füldner and C. Grünsfelder for valuable discussions as well as the entire staff of the ISTC-H84 for device fabrication. A portion of this work was performed within the ESPRIT 24115 ACE project and was supported by the European Union. Also, the excellent collaboration during the ACE Project with Dr. Bourenkov, Dr. Lorenz and Prof. Ryssel from the FhG IIS-B is acknowledged.

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