Bias-stress-induced increase in parasitic resistance of InP-based InAlAs/InGaAs HEMTs
Introduction
InP-based HEMTs are promising devices for over-40-Gbit/s optical communications systems and millimeter-wave applications. Since long-term reliability is an important issue for IC applications, lots of studies have investigated the degradation mechanisms. The shift in the threshold voltage and the kink effect were eliminated by using an InP etch-stop layer and a WSiN gate metal [1]. This is a result of the surface passivation effect of InP [2] and the refractory nature of WSiN [1]. However, the problem of the increase in the parasitic resistances, particularly the drain resistance, under bias-and-temperature (BT) stress still remains. Understanding the underlying physics of the increase in the parasitic resistances is therefore necessary in order to find ways to eliminate them.
The degradation phenomena caused by the contamination of particular atoms, such as hydrogen [3], are serious problems in reliability that must be eliminated. Fluorine is one of these atoms, as reported by Hayafuji et al. [4]. They reported that fluorine atoms combine with silicon atoms and inactivate them in InAlAs [4], [5]. This is a serious problem in InP-based HEMTs because they usually have silicon donors in the InAlAs barrier layer. An InAs/AlAs superlattice for the barrier and/or carrier supply layer [6], [7] and an AlGaAs carrier supply layer [8] have been examined as ways to eliminate the fluorine-induced degradation. Hot carriers are also a cause of degradation. An increase in the drain resistance during BT stress is a degradation phenomenon commonly observed, and it is usually quite larger than the increase in the source resistance.
In this paper, increases in parasitic resistances of 0.1-μm-gate InP-HEMTs due to BT stress were investigated. We employed InP as an alternative carrier supply layer material, and the material dependence of the source resistance increase was studied to ascertain the influence of the fluorine-induced degradation. In addition, BT stress tests were carried out on devices having gate recesses with various lateral depths, and the effects of the size of the gate recess on the increases in the source and drain resistances were examined.
Section snippets
Device structure and experiments
Samples were 0.1-μm-gate InAlAs/InGaAs HEMTs with an InP recess etch-stop layer [1] (see Fig. 1). The heterostructure layer grown by metalorganic chemical vapor deposition consists of an i-InAlAs buffer layer, i-InGaAs channel layer, i-InAlAs spacer layer, Si planar-doped carrier supply layer, i-InAlAs barrier layer, i-InP etch-stop layer, Si-doped InAlAs cap layer, and Si-doped InGaAs cap layer from bottom to top. The source and drain ohmic electrodes are Ti/Pt/Au non-alloyed contacts [1].
Increase in source resistance
The samples with the conventional InAlAs carrier supply layer, i.e., sample (a), were tested under various BT stress conditions. The gate voltage (Vgs) was fixed to 0 V. The source resistance (Rs) was measured using the end-resistance method [9]. The measurement configuration is illustrated in Fig. 2(a). The voltage appearing at the drain terminal (Vch) is regarded as the voltage drop across the source resistance. The current Ig versus Vch is shown in Fig. 2(b). The source ohmic region
Conclusion
In conclusion, the BT-stress-induced degradation of 0.1-μm-gate InP-based HEMTs was investigated. Our data show that the bias-assisted donor passivation by fluorine is a cause of the increase in the source resistance. The increase can be prevented by using In(Al)P for the carrier supply layer. The increase in the drain resistance is associated with different mechanisms of the degradation phenomena. A deep lateral gate recess can suppress the increase in the drain resistance after long BT
Acknowledgements
The authors are grateful to T. Maruyama, T. Kusumoto for the support of the device fabrication, K. Ogawa for the support of BT stress tests, and T. Enoki and H. Fushimi for fruitful discussion. They also thank Y. Ishii and H. Toba for continuous support and encouragement on this work.
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Present address: NTT Advanced Technology Corporation, 3-1 Morinosato Wakamiya, Atsugi, Kanagawa 243-0198, Japan.