Interconnecting to aluminum- and copper-based semiconductors (electroless-nickel/gold for solder bumping and wire bonding)

Abstract

Electroless nickel and immersion gold plating technologies (e-Ni/Au) have traditionally been used almost exclusively within the electronics industry to create a solderable surface on substrate materials, e.g. laminate boards. Recent advances in these plating technologies, along with the inherent low costs associated with electroless plating processes, have enabled the extension of their utilization into a variety of semiconductor applications, e.g. wafer level pad metallization. This paper describes the electroless nickel and immersion gold processes for both aluminum- and copper-based semiconductors. The nickel plating bath is a hypophosphite-based solution and the gold bath is a cyanide-free sulfate-based solution. For aluminum-based integrated circuits a zincation process is used to initiate nickel growth, and for copper, palladium is used to catalyze the surface. Tight control of the chemistries, equipment, and run-time process variables are required to ensure repeatability. Thin film Auger analysis of the as-plated films shows well-defined layers of high purity gold and nickel/phosphorous. Adhesion of the e-Ni/Au layers was evaluated by measuring the load required to shear I/O pads plated with tall nickel bumps. Integrity of the nickel was further evaluated by subjecting the structures to multiple temperature cycles and test for pad shear strength. Results show no degradation in shear load or failure mode.

The deposition of nickel and gold onto the I/O pad surfaces enables the subsequent use of both wire bond and flip chip (lead-based and lead-free alloys) interconnect methods. The integrity of gold wire bonds to the e-Ni/Au plated I/O pad was evaluated using ball shear, wire pull, and the corresponding failure analysis of each. Results show values well above product specifications, with wire pull failure modes in the wire and intermetallic failure in the ball shear studies. For flip chip applications, the e-Ni/Au layer was evaluated using stencil-printing technology to deposit several different solder alloys. In the current investigation, two test vehicles were successfully bumped with both 63Sn/37Pb and 90Pb/10Sn lead-based solder alloys, as well as the 95.5Sn/3.8Ag/0.7Cu lead-free alloy. In order to evaluate the compatibility of these alloys with the electroless nickel layer, solder bump shear tests were performed as a function of number of reflow cycles. Results show no degradation in shear load or failure mode among all three of the alloys tested, indicating no critical nickel consumption (i.e., excessive intermetallic growth) during reflow. Additional tests were performed comparing nickel under-bump-metallurgy (UBM) thicknesses of 1, 2 and 5 μm. Again, no critical nickel consumption was detected.

Introduction

A majority of all integrated circuits have historically been connected to the next layer of packaging (e.g. lead frame, circuit board, and ceramic substrate) using gold or aluminum wire bonds. The techniques and equipment associated with wire bonding have undergone significant advances throughout the years; resulting in increased manufacturing speeds and improved reliability of the bond between the wire and the aluminum I/O pad on the integrated circuit.

Newer interconnect technologies, such as flip chip bumping, are quickly being adopted as an alternative interconnect technique for many applications. Both metal-based solders (e.g. eutectic PbSn, high lead, and lead-free alloys of AgSn) and filled polymer-based materials (e.g. silver filled epoxies and anisotropic adhesives) are currently being used as the interconnect materials for most flip chip applications. The implementation of these flip chip technologies can provide many advantages over wire bonding in terms of cost, electrical performance, I/O density, package size, and reliability [1], [2], [3], [4]. However, one cannot simply apply these flip chip interconnect materials directly onto the aluminum I/O pads of the integrated circuit. A barrier material, such as nickel or chromium, is required to prevent electromigration and brittle intermetallic formation. In addition, a wettable material, such as gold or platinum, is required to allow the formation of a strong interface between the solder and pad metallurgy. Together, these added layers are known as under-bump metullargies (UBMs).

With the recent implementation of copper metallurgy into integrated circuit design, [5], [6] new techniques and materials are required for both of the interconnect technologies mentioned above: wire bonding and flip chip [7], [8]. The use of electroless nickel and immersion gold has been shown to be a universal pad metallization system [9], [10], [11], [12], [13], enabling both wire bonding and flip chip, on both copper- and aluminum-based ICs (Fig. 1).

This paper describes: the technologies related to plating electroless nickel and immersion gold on both copper and aluminum ICs, some of the criteria required for implementation of this technology into volume production, characterization of the nickel and gold layers, wire bonding results, and solder bumping results.