Investigation of a constant behavior of aliasing errors in signature analysis due to the use of different ordered test-patterns in LFSR based testing techniques

Abstract

In this paper, the impact of the change of the order of the test patterns, on error masking behavior of signature analysis scheme used in an linear feedback shift register (LFSR) based testing technique, is investigated. The investigation is carried-out through an extensive simulation study of the effectiveness of an LFSR based testing technique. The results of the simulation study show that the probability of aliasing errors remains unchanged although the changed order of the input test-sequences were applied to the circuit under test.

Introduction

Over the years there has been a remarkable growth in very large scale integration (VLSI) techniques. Tremendous advances in fabrication technologies have led to increased integrated circuit (IC) densities. As a consequence of higher integration densities, circuits have become very complex. To verify their correct functioning, thorough tests are required for ICs. The costs involved in testing of even large scale integration (LSI) chips are a substantial portion of the total manufacturing cost [1], [2], [3]. Further, advances in IC technology are occurring at a rate faster than those in test technology. A direct consequence of this is that those testing methods, which are inadequate even for LSI circuits, are unable to cope with the increased circuit sizes because of higher chip densities [2], [3].

A major problem in testing of large circuits is, the generation of test-stimuli for the achievement of an acceptable level of testing. Conventionally, test-pattern generation and fault simulation mechanisms are intertwined and are continued till the desired fault coverage for the circuit under test (CUT) is achieved [1], [2], [3], [4], [5]. In general, it has been shown that the computational complexity of test-generation is proportional to G_c³ where, G_c is the gate count. Furthermore, the process of fault-simulation is ten times more complex than that of the logic simulation. Also, the complexity of fault-simulation itself grows proportionally to the square of the G_c [1], [2]. These above discussed factors have led to the postulation of alternative strategies and the most successful amongst them has been the design for testability (DFT) approach [1], [2], [3], [4], [5], [6], [7]. The objective of DFT is to integrate the design and test processes leading to circuits, which are inherently testable at minimum cost. i.e. the objective is to follow the rule expressed in Eq. (1), below.

$$\text{Cost}\text{(}\text{design}\text{+}\text{test}\text{)⩽(}\text{Cost}\text{design}\text{+}\text{Cost}\text{test}\text{).}$$

Even with structured DFT methodology, the problem of test-generation through algorithmic means still remains. Coupled with this is the handling of large volume of response data. Both of these factors are the functions of size and complexity of the circuit. One possible solution for this is the approach of built-in test (BIT). The basic idea of BIT is to incorporate the test functions in the hardware itself. This is feasible in view of the availability of larger silicon real estate on the chip. As a natural outcome of the structured design approach for DFT, self-testing has drawn considerable attention. The end result is the built-in self-test (BIST) approach. Currently, BIST has promised to be an effective tool for tackling test problems of VLSI chips and systems [2], [4], [5], [6], [7].

In particular, pseudo-random test pattern (PRTP) generation followed by the compression of response data by signature analysis (SA) has become a standard form of testing in BIST environment [2], [4], [5]. Linear feedback shift registers (LFSRs) have been proposed as an integral part of a sequential logic design, such that they can be used to both generate and compact the results of a test. Undoubtedly, an LFSR based PRTP generation is an extremely simple tool for generating any length of a desired sequence of the test-stimuli. Such a desired sequence of the PRTP can be obtained by the predetermined `initial loading' of the LFSRs. Difficulty arises when the resulting response data obtained from the CUT is compressed into small signatures using SA scheme. Although, this scheme is easily implemented by an LFSR, but this leads to loss of information, due to the erroneous response patterns that gets compressed into the same signature as the fault-free signature of the CUT. Thus, some of the faults might go undetected due to this masking phenomenon. This problem of error masking is called `aliasing' [4].

Methods to determine the extent of fault-escape caused by a response compressor are not readily available. However, various attempts [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23] have been made to analyze and improve the basic signature scheme. The end goal of the above schemes, individually, or with a combination of these, is to reduce the deception volume [9]. Furthermore, a close look of each of the individual techniques, suggested in the research papers [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23] reveals that the level of aliasing errors in LFSR based testing approach may be reduced by implementation of either of the following schemes individually or their combinations. The schemes are:

• Use of primitive characteristic polynomials in the LFSRs of PRTP generators (PRTPGs).

• Use of different ordered PRTPs.

• Use of an incremented bit-length size of LFSR in SA schemes.

• Use of primitive characteristic polynomials in the LFSRs of SA schemes.

In the research papers [11], [16], [18], [19], [20], [21], [23] it is conjectured that the order of the test patterns applied to the CUT may change the level of the probability of aliasing errors. Whereas, this paper, investigates a critical condition in context to the role of different ordered PRTPs on the effectiveness of an LFSR based testing technique. The simulation study made through this paper reveals that the change of the order of the test-patterns do not have any impact on the effectiveness of an LFSR based testing technique i.e. the behavior of fault-masking phenomenon (level of aliasing errors) remains unchanged.