A review of recent MOSFET threshold voltage extraction methods
Introduction
The threshold voltage (VT) is a fundamental parameter for MOSFET modeling and characterization [1], [2], [3], [4], [5], [6]. This parameter, which represents the onset of significant drain current flow, has been given several definitions [7], [8], [9], but it may be essentially understood as the gate voltage value at which the transition between weak and strong inversion takes place in the MOSFET channel. There exist numerous methods to extract the value of threshold voltage [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34], [35], [36], [37], [38], [39], [40], [41] and various extractor circuits have also been proposed [42], [43], [44] to automatically measure this parameter. Recently three books [1], [2], [3] and three articles [4], [5], [6] have reviewed and scrutinized different available methods.
The greater part of the procedures available to determine VT are based on the measurement of the static transfer drain current versus gate voltage (ID–Vg) characteristics [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34], [35] of a single transistor. Most of these ID–Vg methods use the strong inversion region [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], while only a few consider the weak inversion region [28], [29], [30], [31]. Extraction is mostly done using low drain voltages so that the device operates in the linear region [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32], [33]. However, VT extraction with the device operating in saturation is also frequently carried out [34], [35].
A common feature present of most VT extraction methods based on the ID–Vg transfer characteristics is the strong influence of the source and drain parasitic series resistances and the channel mobility degradation on the resulting value of the extracted VT. This situation is highly undesirable because the correct value of the extracted VT should not depend on parasitic components nor mobility degradation. In order to eliminate the influence of these unwanted effects some methods have been proposed which are based on measuring capacitance as a function of voltage [36], [37]. However these C–V methods have the disadvantage of requiring elaborate high-resolution equipment to measure the small capacitances present in MOSFETs, particularly in very small geometry state-of-art devices. Other approaches to eliminate the influence of parasitic series resistances are based on measuring the ID–Vg transfer characteristics of various devices having different mask channel lengths [38], [39], or on measuring several devices connected together [40], [41]. Although such multi-device approaches offer interesting solutions to this problem, they require additional work and the availability of several supplementary special devices. Another recently proposed method that requires repeated measurements is based on a proportional difference operator [26], [27].
The extraction of VT in non-crystalline MOSFETs is more conveniently performed using the drain current in saturation, considering that these devices present much smaller currents than single-crystalline devices. Amorphous and polycrystalline thin film transistors (TFTs) introduce the additional difficulty that the saturation drain current in strong inversion is usually modeled by a power law with an exponent which can differ from 2 [45], [46]. Because of this behavior, using conventional VT extraction methods developed for single-crystal devices will generally produce values of VT that are unacceptable or at least not very accurate. Therefore the extraction method must be capable of extracting the value of the unknown power-law exponent parameter and take it into consideration in the extraction process. To that end, methods have been proposed that are specific for non-crystalline thin MOSFET TFTs [45], [46] and thus allow to extract their threshold voltage correctly.
This article will review and scrutinize the following existing ID–Vg methods for extracting VT in single-crystal MOSFETs, biased in the linear region: (1) constant-current (CC) method, which defines VT as the gate voltage corresponding to a certain predefined practical constant drain current [1], [2], [3], [4], [5], [6], [10], [11]; (2) extrapolation in the linear region (ELR) method, which finds the gate voltage axis intercept of the linear extrapolation of the ID–Vg characteristics at its maximum first derivative (slope) point [1], [2], [3], [4], [5], [6]; (3) transconductance linear extrapolation (GMLE) method, which finds the gate voltage axis intercept of the linear extrapolation of the gm–Vg characteristics at its maximum first derivative (slope) point [19], [20]; (4) second derivative (SD) method, which determines VT at the maximum of the SD of ID with respect to Vg [12]; (5) ratio method (RM), which finds the gate voltage axis intercept of the ratio of the drain current to the square root of the transconductance [13], [14], [15], [16], [17], [18]; (6) transition method [33]; (7) integral method [32]; (8) Corsi function method [21]; and (9) second derivative logarithmic (SDL) method, which determines VT at the minimum of the SD of log(ID)–Vg [31]; (10) linear cofactor difference operator [22] (LCDO) method, and (11) non-linear optimization [23], [24].
This article will also review the following two methods to extract the VT of single-crystalline MOSFETs, operating in the saturation region: (1) extrapolation in the saturation region (ESR) method, which finds the gate voltage axis intercept of the linear extrapolation of the ID0.5–Vg characteristics at its maximum first derivative (slope) point [1], [2]; and (2) G1 function extraction method [34], [35].
Finally, we will review and discuss some amorphous TFT specific procedures which have been recently proposed to extract the threshold voltage of these non-crystalline devices [45], [46].
Section snippets
Extraction from the ID–Vg curve of MOSFETs biased in the linear region
In order to critically assess and compare the different linear region extraction methods reviewed here, we will apply them all to extract the value of the threshold voltage from the measured transfer characteristics of a state-of-the-art bulk single-crystal silicon enhancement-mode n-channel MOSFET with a 5 μm mask channel width, a 0.18 μm mask channel length, and a 32A gate oxide thickness. For this group of methods the device is biased to operate in the linear regime by applying a drain
Extraction from the ID–Vg curve of MOSFETs biased in the saturation region
To extract the saturation threshold voltage VTsat the drain current must be measured as a function of gate voltage with the drain connected to the gate, to guarantee that the device is operating in the saturation regime.
Extraction from the ID–Vg curve of non-crystalline MOSFETs biased in the saturation region
The extraction of VT in non-crystalline MOSFETs is more conveniently performed from the drain current in saturation, considering that these devices present much smaller drain currents than conventional single-crystal bulk devices. Amorphous TFTs introduce the following additional difficulties for VT extraction: First, the saturation drain current in strong inversion is usually modeled by an equation of the form [49]where K is a conductance parameter with units of A V−m and m an
Conclusions
We have presented, reviewed and critically compared several extraction methods currently used to determine the threshold voltage value of bulk single-crystal and non-crystalline thin film MOSFETs from their drain current versus gate voltage transfer characteristics measured either in linear or saturation operation regimes. The relative performance of the presented methods was illustrated and compared under the same conditions by applying them to the measured characteristics of two real test
Acknowledgements
This work was supported by “Universidad Simón Bolı́var”, by CONICIT (Venezuela) through grant S1-98000567, and by CONACYT (Mexico), project N1 34400-A.
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Also at: Department of Electronics Science and Technology, Huazhong University of Science and Technology, Wuhan 430074, P.R. China.