A review of recent MOSFET threshold voltage extraction methods

Abstract

The threshold voltage value, which is the most important electrical parameter in modeling MOSFETs, can be extracted from either measured drain current or capacitance characteristics, using a single or more transistors. Practical circuits based on some of the most common methods are available to automatically and quickly measure the threshold voltage. This article reviews and assesses several of the extraction methods currently used to determine the value of threshold voltage from the measured drain current versus gate voltage transfer characteristics. The assessment focuses specially on single-crystal bulk MOSFETs. It includes 11 different methods that use the transfer characteristics measured under linear regime operation conditions. Additionally two methods for threshold voltage extraction under saturation conditions and one specifically suitable for non-crystalline thin film MOSFETs are also included. Practical implementation of the several methods presented is illustrated and their performances are compared under the same challenging conditions: the measured characteristics of an enhancement-mode n-channel single-crystal silicon bulk MOSFET with state-of-the-art short-channel length, and an experimental n-channel a-Si:H thin film MOSFET.

Introduction

The threshold voltage (V_T) is a fundamental parameter for MOSFET modeling and characterization [1], [2], [3], [4], [5], [6]. This parameter, which represents the onset of significant drain current flow, has been given several definitions [7], [8], [9], but it may be essentially understood as the gate voltage value at which the transition between weak and strong inversion takes place in the MOSFET channel. There exist numerous methods to extract the value of threshold voltage [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34], [35], [36], [37], [38], [39], [40], [41] and various extractor circuits have also been proposed [42], [43], [44] to automatically measure this parameter. Recently three books [1], [2], [3] and three articles [4], [5], [6] have reviewed and scrutinized different available methods.

The greater part of the procedures available to determine V_T are based on the measurement of the static transfer drain current versus gate voltage (I_D–V_g) characteristics [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34], [35] of a single transistor. Most of these I_D–V_g methods use the strong inversion region [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], while only a few consider the weak inversion region [28], [29], [30], [31]. Extraction is mostly done using low drain voltages so that the device operates in the linear region [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32], [33]. However, V_T extraction with the device operating in saturation is also frequently carried out [34], [35].

A common feature present of most V_T extraction methods based on the I_D–V_g transfer characteristics is the strong influence of the source and drain parasitic series resistances and the channel mobility degradation on the resulting value of the extracted V_T. This situation is highly undesirable because the correct value of the extracted V_T should not depend on parasitic components nor mobility degradation. In order to eliminate the influence of these unwanted effects some methods have been proposed which are based on measuring capacitance as a function of voltage [36], [37]. However these C–V methods have the disadvantage of requiring elaborate high-resolution equipment to measure the small capacitances present in MOSFETs, particularly in very small geometry state-of-art devices. Other approaches to eliminate the influence of parasitic series resistances are based on measuring the I_D–V_g transfer characteristics of various devices having different mask channel lengths [38], [39], or on measuring several devices connected together [40], [41]. Although such multi-device approaches offer interesting solutions to this problem, they require additional work and the availability of several supplementary special devices. Another recently proposed method that requires repeated measurements is based on a proportional difference operator [26], [27].

The extraction of V_T in non-crystalline MOSFETs is more conveniently performed using the drain current in saturation, considering that these devices present much smaller currents than single-crystalline devices. Amorphous and polycrystalline thin film transistors (TFTs) introduce the additional difficulty that the saturation drain current in strong inversion is usually modeled by a power law with an exponent which can differ from 2 [45], [46]. Because of this behavior, using conventional V_T extraction methods developed for single-crystal devices will generally produce values of V_T that are unacceptable or at least not very accurate. Therefore the extraction method must be capable of extracting the value of the unknown power-law exponent parameter and take it into consideration in the extraction process. To that end, methods have been proposed that are specific for non-crystalline thin MOSFET TFTs [45], [46] and thus allow to extract their threshold voltage correctly.

This article will review and scrutinize the following existing I_D–V_g methods for extracting V_T in single-crystal MOSFETs, biased in the linear region: (1) constant-current (CC) method, which defines V_T as the gate voltage corresponding to a certain predefined practical constant drain current [1], [2], [3], [4], [5], [6], [10], [11]; (2) extrapolation in the linear region (ELR) method, which finds the gate voltage axis intercept of the linear extrapolation of the I_D–V_g characteristics at its maximum first derivative (slope) point [1], [2], [3], [4], [5], [6]; (3) transconductance linear extrapolation (GMLE) method, which finds the gate voltage axis intercept of the linear extrapolation of the g_m–V_g characteristics at its maximum first derivative (slope) point [19], [20]; (4) second derivative (SD) method, which determines V_T at the maximum of the SD of I_D with respect to V_g [12]; (5) ratio method (RM), which finds the gate voltage axis intercept of the ratio of the drain current to the square root of the transconductance [13], [14], [15], [16], [17], [18]; (6) transition method [33]; (7) integral method [32]; (8) Corsi function method [21]; and (9) second derivative logarithmic (SDL) method, which determines V_T at the minimum of the SD of log(I_D)–V_g [31]; (10) linear cofactor difference operator [22] (LCDO) method, and (11) non-linear optimization [23], [24].

This article will also review the following two methods to extract the V_T of single-crystalline MOSFETs, operating in the saturation region: (1) extrapolation in the saturation region (ESR) method, which finds the gate voltage axis intercept of the linear extrapolation of the I_D^0.5–V_g characteristics at its maximum first derivative (slope) point [1], [2]; and (2) G₁ function extraction method [34], [35].

Finally, we will review and discuss some amorphous TFT specific procedures which have been recently proposed to extract the threshold voltage of these non-crystalline devices [45], [46].