Reliability issues of silicon LSIs facing 100-nm technology node

Abstract

Reliability issues regarding scaled silicon devices are reviewed from the viewpoint of the 100-nm technology node. Topics covered include hot carrier degradation, negative bias-temperature instability, boron penetration, interface properties of a high-k dielectric film, and stress-induced leakage current of a floating-gate-type non-volatile memory. Soft error by terrestrial neutrons is also discussed as an emerging reliability issue. In addition, copper-wiring reliability is extensively reviewed from the viewpoint of further miniaturization.

Introduction

LSI manufacturers have been suffering from an unprecedented business slump due to a nosedive of chip prices and a weak demand for PCs and mobile phones. This serious situation is forecast to last for a few years. What manufacturers must do now to deal with this crisis is to reduce the chip cost. So far, microfabrication technology has played an important role in cost reduction by reducing chip size. However, device miniaturization has been becoming increasingly difficult with ever decreasing device size. For example, advanced 256-Mb DRAMs have been manufactured using a 150-nm pattern size and a 130-nm-node CMOS device requires the gate length of less than 100 nm. These sizes are much smaller than the resolution limit achieved by current KrF lithography, even if various resolution-enhancement techniques are used. Thus, further reductions in pattern size do not always bring cost reduction, rather they cause cost increases due to additional investments and possible yield deterioration.

However, from the viewpoints of performance improvement and power reduction, device miniaturization is still demanded. In addition, the growth of systems on chip (SOC) is considered to be an important field for which device miniaturization will be requisite. SOC has been expected to play a major role in various fields such as networks, mobile telecommunication, and digital home appliances. In fabricating the SOC, several kinds of devices must be implemented on the same chip simultaneously. In the 100-nm era, CMOS devices with a gate length around 60 nm, multi-level-thickness gate-oxide films, SRAM, and non-volatile memory will be implemented. DRAM implementation will also be inevitable.

To produce SOC systems in the 100-nm era, both devices and fabrication processes must be reliable and robust enough to enable the implementation of the various kinds of devices. In this paper, several reliability issues arising from advanced CMOS devices and copper wiring are focused on. Recent topics such as soft error caused by cosmic-ray irradiation and topics related to high-k gate dielectric films are also discussed.