DRAM reliability

Abstract

Dynamic random access memory (DRAM) reliability is investigated for future DRAMs where small geometrical devices are used together with new materials and novel process technologies. Among the several items of DRAM reliability, the most important aspect to consider for DRAM reliability is infant mortality which is caused by process-induced defects including random defects. Since the process-induced defects are strongly dependent on process technology, it is inevitable to minimize process-induced defects by developing new process technology. However, whenever new process technology is introduced, new screening techniques or methods are necessary for suppressing infant mortality. The degradation of pMOSFET due to buried-channel pMOSFET during burn-in stress and soft error rate due to α-particle and cosmic ray irradiation become concerns as device dimension shrinks. However, it cannot be limitations of DRAM reliability because pMOSFET degradation due to hot electron induced puchthrough can be suppressed by new layout of pMOSFET, and the soft error events can be overcome by soft error resistant device structure and proper material choices. From these considerations, it can be expected that the advances of DRAM technology generation not only improve the device performance but also enhance the reliability.

Introduction

Dynamic random access memory (DRAM) has advantages of realizing high density due to its simple cell structure of 1T1C (one transistor one capacitor). The density of DRAM has been approximately quadrupled every three years by virtue of advances of DRAM technology. As a result, 256 Mb DRAM is now in full production mode with 0.15 μm DRAM technology generation, 512 Mb DRAM is now in pre-production mode with 0.13 μm DRAM technology node, and sub-0.13 μm DRAM technology is under development in R&D center.

As the device dimension decreases, short channel effect (SCE) becomes much serious. In order to reduce the SCE, complementary metal oxide silicon (CMOS) technology is driven for developing shallow junction, thin gate oxide, halo source/drain implantation and high channel doping. At the same time, thinner metal width with design rule shrinkage results in higher current density [1], [2]. All of these are detrimental to reliability such as oxide quality, hot carrier effect, electrostatic discharge, latch up, metal electro-migration, and so on. The silicon devices fabricated with CMOS technology whether they are logic devices or memory devices, cannot be free from most of these issues.

Since DRAM is composed of memory cell array where bits of 1T1C are formed with two-dimensional matrix, and peripheral area where CMOS control circuit and random logic are formed, reliability of DRAM is determined by both memory cell array and CMOS periphery. The reliability of DRAM due to CMOS periphery can be shared with that of typical CMOS periphery and it has not been a primary concern in DRAM reliability because relaxed CMOS design rule has been used in DRAM periphery. Hence, the reliability of DRAM has been governed by the memory arrays where smallest physical dimension is always used together with highest applied voltage. As the DRAM technology generation enters sub-0.13 μm node, many challenges emerge from not only reliability aspects but also technological aspects. The challenges from technological aspects are well studied, and their solutions for challenges are under development [3], [4]. On the other hand, the challenges from reliability aspects have not been properly studied, even though they are essential for commercial products. In this paper, the reliability of DRAM, mainly determined by the memory cell, will be discussed, and it will be predicted for future scaled down DRAMs.

The origins of DRAM reliability can be categorized into three critical failures. The first is the field failure (failure during operation by customer) induced by defects such as word line-bit line leakage or capacitor dielectric leakage current [5]. The second is the failure induced by electrical or temperature stress [6]. The last is the failure induced by soft error event from α-particle and cosmic ray radiation effect [7], [8], [9], [10], [11]. Reliability problems induced by defects are mostly related with infant mortality, which is the most important in DRAM reliability. The failures induced by electrical or temperature stress are important for estimating useful lifetime and determining burn-in condition to guarantee a device lifetime. The soft error rate (SER) is important in space-applications such as satellite and spacecraft and it will be more important in future because of more prevalent applications of space.

Another important topic in DRAM reliability is a screening procedure. Most of failure due to infant mortality can be screened out by wafer burn-in or package burn-in tests [12], [13]. In this paper, three key reliability aspects of DRAM reliability such as infant mortality, device life time and soft error will be discussed with screening methods of those items.