Carrier injection efficiency for the reliability study of 3.5–1.2 nm thick gate-oxide CMOS technologies

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Abstract

The hot carrier (HC) reliability has been investigated in MOSFETs with ultra-thin SiO2 gate-oxide ranging from Tox=3.5 to 1.2 nm and in high speed CMOS technologies in order to identify the worst-case of HC injections. Distinctions are obtained between the influence of the Tox thinning and the shrink of the gate-length with LG ranging from 0.25 to 0.1 μm. Results show that the worst-case of HC damage can be different from the bias condition of the maximum substrate current (IB) in N-channel devices and of the hot electron (HE) injections in P-channel devices with the Tox and LG margin. It is shown that the interface trap generation (ΔNit) has become the main damage mechanism at long term with the use of the correlation between charge pumping analysis and drain current reduction. We focus on the hole injection efficiency, the extension of the degraded region (ΔL) with the LG reduction and the influence of the carrier energy which all participate to the degradation of ultra-thin gate-oxide MOSFETs submitted to carrier injections.

Introduction

With the down scaling of CMOS technologies below the 100 nm gate-length and under 1 V supply voltage, the device reliability becomes more dependent on the carrier injection mechanisms and defect generation [1], [2]. The excellent SiO2 scaling possibilities which enable the SiO2 thickness to reach 1.5–1.2 nm is still the key material for gate-oxide used in actual MOSFETs and for future CMOS generations [3] but its thickness limit becomes questionable regarding the trade-off between power consumption, performances and circuit reliability. Apart from destructive experiments allowing to study the statistical properties of time or charge to breakdown, electrical stresses can be used to study the progressive build-up of defects responsible for the wear-out of the structure. This can be determined using uniform injections of carriers or localized hot carrier injections generated either in the channel or in the substrate and eventually involving the secondary impact ionization (2I) phenomenon [4], [5] with the bias in the substrate VB. By reducing the gate-oxide thickness (Tox) and increasing the complexity of the device processing, the channel hot carrier (CHC) reliability becomes strongly dependent on the dielectric quality, the proportion of the degraded length with respect to the channel length and the technology generation [6], [7]. In that later case, the optimisation of the drain architecture may significantly influence the impact of the degradation mechanism on the transistor parameter [6] depending on the doping level of the retrograde well and the presence of pocket implants [8].

Section snippets

Device fabrication and experimental techniques

The devices used in this study were N- and P-MOSFETs with dual n+/p+ polysilicon gates. Devices from a 1 μm technology (Tech. A) compatible with a 50 nm CMOS technology is specifically used to study the influence of the Tox thinning in the 3.5–1.2 nm range with a standard LOCOS isolation, RTO-SiO2 thermal oxide and LDD architecture with As-implanted source and drain using standard RTA and post metallization annealing. Devices from a technology B (Tech. B) were devoted to study the device

Gate-oxide thickness dependence

The degradation kinetics of the saturated drain current ID are shown as a function of the gate injected charge QINJ in Fig. 1 and as a function of the bulk ionization charge QB in Fig. 2. QB, which is representative of the number of hot-carriers, is obtained by integrating the substrate current during the stress. As the proportion of tunneling carriers towards the gate terminal strongly increases with the Tox reduction, the effect of IB stressing on the drive current reduction for a fixed 10

Summary and conclusions

The HC injection efficiencies have been distinguished in ultra-thin oxide devices and very short-channel devices. As charge trapping disappears, the worst-case of HC damage is due to ΔNit which becomes more dependent on the HC number (QB), their energy, the length of the degraded region ΔL but not on the Tox reduction. In N-channel MOSFETs the ΔL impact is found for the worst-case at the 2I condition in very thin gate-oxide (1 μm) devices with standard LDD architecture and under HE condition

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