Hot-Spot Meaurements and Analysis of Electro-Thermal Effects in Low-Voltage Power-MOSFET’s

In every new technology, the understanding of its failure mechanism is essential to ensure reliability. In this paper an overview on some state-of-the-art characterization methods of 4H-SiC metal oxide semiconductor field effect transistors (MOSFETs) are presented. Silicon-based devices employ many different tools for the study of failure mechanism, which can be exploited for silicon carbide (SiC) devices. Silicon carbide semiconductor offers very interesting electrical and thermal properties for power electronics application in comparison to Si but exhibits different failure mechanisms that need to be studied. Silicon carbide MOSFETs allow for a better energy conversion efficiency in comparison to silicon-based devices, with potential applications in electric vehicles and microgrids converters. Silicon carbide technology can greatly improve on electrical energy management and so failure mechanism studies will lead to the production of robust and high performance devices.

The aim of this paper is to provide an extensive overview about the state-of-art commercially available SiC power MOSFET, focusing on their short-circuit ruggedness. A detailed literature investigation has been carried out, in order to collect and understand the latest research contribution within this topic and create a survey of the present scenario of SiC MOSFETs reliability evaluation and failure mode analysis, pointing out the evolution and improvements as well as the future challenges in this promising device technology.

In this paper we experimentally demonstrate that SiC high voltage Power MOSFTEs exhibit an unstable electro-thermal behavior for given electrical conditions, depending on the chip thermal impedance. This instability can lead to hot-spot formation and eventually thermal runaway whit subsequent device destruction after a stressful short-circuit. The analysis was carried out on a commercial 1.2 kV SiC Power MOSFET by investigating the device electro-thermal behavior in short-circuit operation with a state-of-art IR thermographic set-up. By biasing the device at different gate voltages, the stable and unstable regions are evidenced with electrical and thermal measurements. Finally an unstable behavior is triggered and an hot-spot coherent with the failure location is demonstrated.

Silicon carbide (SiC) power MOSFETs are characterised by potentially thermally unstable behaviour over a broad range of bias conditions. In the past, such behaviour has been shown for silicon (Si) MOSFETs to be related to a reduction of Safe Operating Area at higher drain–source bias voltages. For SiC MOSFETs no characterisation exists yet. This paper presents a thorough experimental investigation for devices of different voltage classes (600 and 1200 V) and different manufacturers, highlighting important differences in electro-thermal performance and failure mode as compared to Si devices. The goal is to derive information for design optimisation and reliable device development for a diverse range of target applications.

This paper focuses on optimization of bond wire positions as a method to improve thermal management of power semiconductors. For this purpose, robustness of a new low-voltage MOSFET generation with an optimized multiple bond wire arrangement and device shape is compared to an older device design with lower number of bond wires. 2D electrical simulation is used to evaluate the lateral distribution of power dissipation due to the gate voltage de-biasing effect. 3D thermal finite element simulation and infrared thermography measurements are employed to analyze the corresponding surface temperature distribution. Finally, tests under extreme single pulse short-circuit conditions demonstrate the effectiveness of thermal management for improving robustness in automotive applications.

Electro-thermal destruction of n- and p-channel lateral double-diffused MOS in smart power ICs is investigated by electrical pulse experiments, simulations and failure analysis. It was observed experimentally and by TCAD simulation that the location of the hot spot plays very important role for single pulse energy capability. Damage both in silicon and copper metallization was observed. The n-DMOS exhibits better energy capability compared to p-DMOS due to better cooling efficiency of silicon area by the copper metallization. Effect of drift region length, doping profile and of copper metal thickness on energy capability is also analyzed.