A high speed scheduler/controller for unbuffered banyan networks
Introduction
The advent of packet switched techniques to integrate the transport of data from different applications and the concurrent increase in network bandwidth has heightened the need for high speed communication switches. Multistage interconnection networks (MINs) such as banyan networks have been widely investigated for use in these switches. A banyan network connecting N input ports to an equal number of output ports can be constructed using 2×2 switches. However, contention for these switches prevents a banyan network from providing simultaneous connections for all possible permutations of connections between input and output ports. This blocking characteristic limits the performance that can be obtained from a single banyan network.
A wide variety of banyan-based network architectures have been developed to overcome the performance limitations imposed by blocking [12]. Many designs place control logic in the switches to buffer and/or route packets. Packets which cannot be routed correctly due to contention may be dropped or passed through the switch fabric using deflection routing [13]. Packets, which exit the network at an incorrect destination, are not delivered, but are instead discarded or rerouted. A key performance measure of these designs is the rate at which packets must be discarded.
The loss rate can be reduced by using multiple banyan networks. For example, replicated architectures distribute the workload across several networks placed in parallel [1], [6]. Tandem architectures place banyan networks in a series [13]. Dilated architectures increase the number of links between switches in the banyan [6]. These architectures have been enhanced by interconnecting replicated or tandem networks using dilated links [15] or bypass connections [4]. An approach that can reduce packet loss with a minimal increase in the amount of hardware is to recirculate packets back into the network that would otherwise be lost [14]. Recirculation has been incorporated into many of these designs [11], [13].
Similarly, parallel networks have been used to increase the bandwidth of the switch fabric. Four switching planes with a one byte interface are used in Ref. [2] to handle input line speeds of up to 2.4 Gb/s. The switch described in Ref. [7] uses a selectable number of parallel one-bit wide cross-bars to improve switch throughput. Optical switch fabrics may provide another means of obtaining high bandwidth, where parallelism can be provided through wavelength division multiplexing (WDM). The use of electronic control logic in the switch elements may greatly reduce the performance of such an optical network, however.
The focus of this paper is to describe a high speed controller that can be used with a variety of banyan network switching fabrics, where the fabric provides the required bandwidth using simple 2×2 switches that do not have buffers or control logic. This means that connections between input ports and output ports are managed with centralized, circuit-switching techniques. The proposed controller could control a single high speed, highly reconfigurable optical banyan network built from electro-optical switches to provide all-optical paths through the switch fabric [10]. Alternatively, the switch fabric could be a replicated architecture consisting of electronic, unbuffered, banyan networks. Controller design parameters can be adjusted to provide operational and performance characteristics that are similar to those of parallel, tandem, and recirculating banyan architectures.
Central control has been used in other communication switch architectures. For example, a centralized scheduler for a cross-bar based switch fabric is described in Ref. [7], and a centralized algorithm for control of a MIN is described in Ref. [9]. With the centralized approach, the controller accepts a set of requests from the input ports for connections to output ports. The requests are processed to identify a contention-free subset. This information is returned to the input ports as authorization to transmit packets through the switch. Since packets are not transmitted until the desired connection is available, requests that are not granted are resubmitted [3], rather than recirculated.
During request processing, the controller can also determine the state required at each switch to establish the selected connections. When this network state information is used to set the states of the switches prior to data transmission, the proposed device acts as a switch controller. When it is not necessary to set the network state, the device acts as a transmission scheduler. The techniques used to determine the network state for unicast connections can be extended in a natural way to handle multicast.
To provide satisfactory performance, the controller must be capable of determining non-conflicting sets of connection requests at a rate sufficient to handle the requests arriving from the input ports. The controller can be pipelined to provide successive network states in constant time, independent of the number of ports. Since the states developed by the controller provide connections for a contention-free set of requests, the blocking characteristics of the banyan network affect the performance of the controller, rather than that of the switch fabric. The switch fabric can therefore be chosen based on the required bandwidth. Different controller implementations can be used to provide the switch with performance characteristics that are similar to those of replicated, tandem, and recirculating banyan architectures.
The rest of the paper is organized as follows. In Section 2, we describe connection requests and their processing. We show how this can be extended to include multicast operations in Section 2.5. We describe the hardware design and considerations for pipelining the controller is Section 3, and present some performance results in Section 3.2 before concluding in Section 4.
Section snippets
Centralized control of a banyan network
A banyan network is a class of multistage interconnection networks (MIN) that provides a unique path from any input port to any output port. A banyan with N=2n input ports can be built with 2×2 switches using n stages of N/2 switches. An example of a banyan network with a reverse cube interconnection pattern for N=8 is shown in Fig. 1. Data transmitted by an input port may pass through a well-defined subset of the switches in the network. The switches that can be used for data transmitted by
Controller performance
The controller's design distributes the logic used to resolve contention and establish connections. There is no single, central component which has knowledge of all the connection requests and which can optimize the number of connections provided by a network state. The key to obtaining good performance with this design is for the controller to resolve contention and develop network states quickly and for the switch fabric to control the internal switches and transmit data at a commensurate
Conclusions
We have described an architecture for the central controller of a network switch based on a banyan architecture. The controller uses a hierarchical approach to resolving contention for the state of the switches in the network. The logic required to resolve contention can be built into fast hardware, and can be easily pipelined. This means the controller can create network states that provide contention-free connections through the switch in constant time, independent of the number of switch
Acknowledgements
This work is supported in part by NSF award MIP-9633729 to the University of Pittsburgh.
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