An efficient packet service algorithm for high-speed ATM switches

Abstract

The unprecedent development of the World Wide Web, and the emerging of new types of applications such as video-on-demand and teleconferencing put an increasing pressure on the communication infrastructure. One of the main components that directly determine the communication bandwidth and the quality of services that are provided are the communication switches. In this paper, we propose a new scheduling algorithm for servicing the output sessions of a high-speed ATM switch that is both accurate and efficient. To each session we associate a weight w that represents the share of the communication bandwidth it should receive. To characterize the allocation accuracy we give bounds for the difference (called lag) between the number of time slots that each session should receive and the number of time slots it actually receives. Specifically, we show that in the particular case in which the aggregate weight W over all sessions is a power of two, the lag of a session with weight w is bounded by O(ones(w)), where ones(w) represents the number of ones in the binary representation of w. In the general case in which the aggregate weight has an arbitrary value, we show that the session's lag is bounded by O(log w). The selection of the session to be serviced during the next time slot takes O(log log W). We also propose a simple hardware implementation that reduces the selection time complexity to O(1). Finally, we discuss the application of our algorithm in the context of both work-conserving and non-work-conserving disciplines.

Introduction

With the exponential growth of the Internet traffic, and with the development of new types of multimedia applications that require both large bandwidth and service guarantees, the necessity of designing high performance switches becomes more and more important. Since ATM seems to become the standard of choice for future high-speed networks, in this paper we propose a new weighted fair-queueing scheme for ATM switches, which is both accurate and efficient.

To each session we associate a weight that represents the relative share of the bandwidth the session should receive. Two of the main parameters used in characterizing many allocation algorithms are the accuracy and efficiency. The accuracy is measured in terms of the difference between the service time that a session should receive in an idealized system in which the service time is allocated in arbitrarily small increments, and the service time that the session actually receives. By bounding this difference, called service lag, it is theoretically possible to derive bounds for the delay and the loss probability of a session, once the shape of the incoming traffic is known. We note that previous studies of the idealized system, such the one of Zhang et al. [1], can be used as starting points in deriving such bounds. Another major concern in developing a scheduling scheme for a high-speed ATM switch is its efficiency. This is simply because the transmission time of a cell, during which the selection of the next session is usually done, is very short. For example, for a 1 Gb/s switch, this time is about 0.4 μs.

Previously proposed solutions have demonstrated the two-way tension between the allocation accuracy, and the implementation efficiency. For example, while the newly developed weighted fair-queueing algorithms, such as WF²Q [2]and EEVDF [3], achieve optimal constant lag bounds, their implementation makes use of priority queues, which exhibit an O(log n) time complexity, where n represents the number of active sessions. Unfortunately, in a real system, where the number of sessions can be of the order of tens or hundreds of thousands, a software implementation is not feasible, while a hardware implementation may be expensive due to the high complexity of supporting priority queues. On the other hand, to the best of our knowledge, the existing weighted fair algorithms that can be efficiently implemented (such the ones based on the round-robin scheme 4, 5) do not guarantee lag bounds better than O(n).

In this paper we propose a new scheduling algorithm that can be both efficiently implemented, and guarantees low lag bounds. More precisely, our algorithm guarantees that in the particular case in which the aggregate weight of all sessions is a power of two, the lag bound of any session with weight w is bounded by O(ones(w)), where ones(w) represents the number of ones in the binary representation of w. We note that when the switch bandwidth can be expressed as a power of two, this result gives us tight bounds for the session's lag in the worst case, when all the switch bandwidth is allocated (see Section 6for details). In the general case in which the aggregate weight can have an arbitrarily value we show that the session's lag is bounded by O(log w). In addition, our algorithm can be efficiently implemented in software in O(log log W_total), where W_total represents the switch bandwidth expressed in some basic allocation units. For example, in the case of a 1 Gb/s ATM switch, whose bandwidth is allocated in increments of 1 Kb/s, log log W_total is as low as 5.¹ Moreover, we propose a straightforward hardware implementation, that can perform the selection of the next session to be serviced in constant time.

The remainder of this paper is organized as follows. Section 2presents a new proportional share allocation algorithm, called bit reversal (BR). Based on the BR algorithm, Section 3proposes a hierarchical scheme (called HBR), which reduces the time complexity of the session's selection procedure. Further, Section 4proposes a simple hardware implementation of the HBR scheme in which the selection operation can be performed in constant time. Section 5discusses possible implementations of both work-conserving and non-work-conserving policies, by using the HBR scheme. Section 6presents the lag bounds for both BR and HBR and discusses their implications. Finally, Section 7presents the related work, while Section 8concludes the paper.