A functional-level testability measure for register-level circuits and its estimation

https://doi.org/10.1016/S0141-9331(98)00111-2Get rights and content

Abstract

Estimation of circuit testability is an important issue when evaluating the circuit design. A testability measure indicates how easy or difficult it would be to generate tests for the circuit. STAFAN (Statistical Fault Analysis) is a well known gate-level testability analysis program which predicts the fault coverage of a digital circuit under the stuck-at fault model, without actually performing fault simulation. STAFAN offers speed advantage over other testability analysis programs such as SCOAP; further, it explicitly predicts the fault coverage for a given test set, unlike other testability measures which are harder to interpret. We show how a STAFAN-like testability analysis program can be constructed for circuits built out of register-level modules such as adders, multipliers, multiplexers, and busses. Our tool, which we call FSTAFAN, is useful in a testability-driven high-level synthesis environment. We have implemented FSTAFAN on a Sun/SPARC workstation and describe its performance on some register-level circuits.

Introduction

It is becoming increasingly important to define a testability measure for a circuit composed of register-level components such as parallel adders, multipliers, registers, counters, multiplexers, and busses. With the proliferation of high-level synthesis softwares for digital systems, it is becoming common practice to design circuits using register-level components. Further, stress is now being laid on incorporating testability at the stage of high-level synthesis. Since high-level synthesis programs explore a large design space, it is useful to have a fast and accurate testability measure which works on register-level components; with such a tool, it becomes possible to reject inferior designs at an early stage of design. Designs are characterized by three components–area A, delay D, and testability T which are indicators of the cost, performance, and testability of the design. While many estimators for area and performance are reported in the literature (see [10]), there are not many testability measures reported for this level of abstraction. Presently, the testability measure being employed at the register-level is the number of self-loops in the structure graph of the circuit. The structure graph is a directed graph constructed by associating a node with each register in the circuit and associating a directed edge from node i to node j when there exists a combinational path from the output of register i to the input of register j [4]. A self-loop in the structure graph represents a “self adjacent” register [1]; when built-in self-test is employed using BILBO architecture [8], a self adjacent register R must be configured both as a PRPG (Pseudo Random Pattern Generator) and an MISR (Multiple Input Signature Register) – an impossibility when concurrent BILBOs are not available. Therefore, most testability-driven synthesis tools attempt to eliminate the number of self-loops in the structure-graph of the final design [12], [1], [9]. Clearly, there are limitations to this testability measure.

  • The testability measure is only appropriate for specific test methodologies such as BILBO-based built-in self-test.The testability properties of the combinational logic blocks in the circuit are ignored by the metric.

When gate-level circuits are concerned, a number of accurate testability measures are known. Popular among these are SCOAP (Sandia Controllability and Observability Program) proposed by Goldstein [5], STAFAN (Statistical Fault Analysis) proposed by Jain and Agrawal [6], and PREDICT (Probabilistic Estimation of Digital Circuit Testability) proposed by Seth and Agrawal [14]. SCOAP uses the controllability and observability of nodes to measure the testability of a circuit. Primary inputs are fully controllable and primary outputs are fully observable. Three numerical measures are associated with each node in a combinational circuit – the combinational 1-controllability CC1, combinational 0-controllability CC0, and combinational observability CO. In a sequential circuit, three other measures are associated with each node, corresponding to sequential testabilities. Goldstein gave simple rules to compute the controllabilities of internal nodes and primary outputs by traversing the circuit forward from the inputs to the outputs in a breadth-first manner [5]. The sum of the six testability measures of all nodes is the testability metric for the whole circuit; the smaller this value, the more testable the circuit.

The advantage of the SCOAP metric is that it measures testability as a topological property of the circuit, without regard to a set of test vectors. In survey of testability measures, Chandra and Patel [3] found that SCOAP comes closest to measuring the true testability of a circuit i.e. there is strong correlation between the fault coverage of a circuit and its SCOAP value. Ravikumar and Joshi have given a fast algorithm to compute the SCOAP values from a hierarchical netlist [11]. STAFAN estimates the fault coverage of a circuit under a given test set without actually performing fault simulation.

Signal probabilities were used in computing the random-pattern testability of a circuit [14], [13]. The signal probability of a line l is the probability that a 1 is placed on line l when exhaustive testing is employed. Simple algebraic rules can be applied to compute the signal probabilities at the outputs of logic gates, given the signal probabilities at their inputs. For instance, if pA and pB are the signal probabilities at the inputs of an AND gate, then the signal probability at the output C is simply pC =pA·pB. In a circuit without reconvergent fanout, these algebraic rules can be applied starting from the primary inputs and traversing the circuit in a breadth-first manner. For general circuits, however, computing the signal probabilities is an NP-complete problem [14]. The signal probability at a line l is related to the probability of detecting a stuck-at fault at line l [14], [13]. Both [14] and [13] gave efficient algorithms for computing the signal probabilities in a combinational circuit.

The 0-controllability C0(l) of a line l in a circuit is defined as the probability that a random test vector places the logic value 0 on the line l. The 1-controllability C1(l) is similarly defined. B0(l), the 0-observability of a line l, is the probability that the logic value on l can be observed at one of the primary outputs, given that this logic value is 0. Thus B0(l) is the conditional probability that there is a sensitized path from l to one of the primary outputs, given that the value on l is 0 when a random test vector is applied. The 1-observability of l, B1(l), is similarly defined. It is possible to compute the detection probability df of a fault stuck-at f on line l, given the controllabilities and observabilities at line l. For instance, the probability of detecting a fault l stuck-at 0 is given bydl−sa−0=C1(l)·B1(l)

STAFAN gives us a method of computing the controllabilities and observabilities of each line in a gate-level circuit by simulating the circuit on N test vectors [6]. Thus logic simulation is used to count the number of times a 1 appears on a line l when each of the N test vectors is applied. The Ones-count at l can be used to compute C1(l) as follows.C1(l)=OnesCount(l)N

If we compute the detection probabilities for all the stuck-at faults in the circuit, we can compute the fault coverage of the circuit for the test set of N vectors. The probability that none of the N test vectors can detect a fault f=ls-a-v is given by (1−df)N and the probability that at least one of the N test vectors will detect fault f is 1− (1−df)N. If F is the set of all relevant stuck-at-faults in the circuit, then the fault coverage using N test vectors isFC=1|F|·fεF1−(1−df)N

STAFAN was applied with success to several benchmark circuits. STAFAN is much less expensive in terms of CPU-time in determining the fault coverage than performing a complete fault simulation.

The testability measures discussed earlier are all intended for gate-level circuits. In this paper, we are interested in developing a testability analysis tool for data paths described at the register-transfer (RT) level. In the next section, we shall discuss the need for testability measures at the RT level. A fault model relevant for RT circuits is then described. A STAFAN-like testability analysis tool (called FSTAFAN) for RT level circuits is developed. Section 3 describes the implementation of FSTAFAN and reports results obtained on several example circuits. Conclusions and directions for further research are presented in Section 4.

Section snippets

Functional testability

In reality, most digital systems are designed using register-level modules rather than gates. If gate-level testing and testability-analysis tools are to be used with practical systems, it would call for an flattening procedure which is expensive both in terms of memory and CPU-time. Frequently, the results of applying testing and testability analysis procedures to building blocks of circuits are available; for instance, the test patterns and SCOAP measures for a 4-bit ripple carry adder may be

Testability of module-external lines

FSTAFAN computes the controllability and observability of each module-external line after the completion of the simulation phase. The one-controllability of a module-external line l is defined as C1(l)=OnesCount(l)/N, where N is the number of test vectors; zero-controllability is similarly defined. The observability O(l) of a module-external line is defined recursively as follows. If l is a primary output, its observability is defined as unity; otherwise, the line l may be observable implicitly

Estimation of fault coverage

After computing the observability and controllabilities of module-external lines, we compute the detection probabilities of each stuck-at fault. Fault coverage is then estimated using Eq. 3. For further details, we refer to Section 1.1 and to [6].

Implementation and results

FSTAFAN was implemented on a Sun–SPARC workstation in C programming language. The complete software requires about 3500 lines of code. The input to FSTAFAN is read from a text file containing the description of the circuit composed of modules such as n-bit adders, multipliers, registers, multiplexers, and basic gates. The user has the option to estimate either the random-pattern testability of the circuit or the fault coverage achieved by a specified test set. The output of FSTAFAN is an

Conclusions

We have presented a Statistical Fault Analysis tool called FSTAFAN that borrows ideas from STAFAN [6] and extends them to circuits composed of macro blocks. FSTAFAN is applicable to technology-mapped circuits and data paths. It is also applicable to mixed-level circuits. FSTAFAN can provide significant speedups in the estimation of fault coverage without too much loss of accuracy when the number of test vectors is large. We have described an implementation of FSTAFAN and results obtained using

Acknowledgements

We acknowledge initial discussions with Vikram Saxena, presently with Department of Electrical and Computer Engineering, University of Illinois, Urbana–Champaign. Thanks are also due to the two anonymous referees whose comments helped us in improving the paper.

Nitin Agrawal received his B. Tech. in Electrical Engineering from the Indian Institute of Technology, Delhi (1995). His B. Tech. thesis was in the area of Modular and Functional Level Testing of VLSI Circuits. He is presently working as a Member, Technical Staff at Software and Silicon Systems (India) Pvt. Ltd. His current area of interests are in the areas of Microprocessor Architecture, High Performance VLSI design techniques and High Level Testing of VLSI circuits.

References (14)

  • L. Avra, Allocation and assignment in high-level synthesis for self-testable data paths, In Proceedings of...
  • J.D. Calhoun et al.

    A framework and method for hierarchical test generation

    IEEE Transactions on Computer-Aided Design

    (1992)
  • S.J. Chandra et al.

    Experimental evaluation of testability measures for test generation

    IEEE Transactions on CAD

    (1989)
  • K.-T. Cheng et al.

    A partial scan method for sequential circuits with feedback

    IEEE Transactions on Computers

    (1990)
  • L.H. Goldstein

    Controllability/observability analysis of digital circuits

    IEEE Transactions on Circuits and Systems

    (1979)
  • S.K. Jain et al.

    Statistical fault analysis

    (1985)
  • M. Jamoussi et al., A new variable testability measure: a concept for data-flow testability evaluation, In Proceedings...
There are more references available in the full text version of this article.

Cited by (0)

Nitin Agrawal received his B. Tech. in Electrical Engineering from the Indian Institute of Technology, Delhi (1995). His B. Tech. thesis was in the area of Modular and Functional Level Testing of VLSI Circuits. He is presently working as a Member, Technical Staff at Software and Silicon Systems (India) Pvt. Ltd. His current area of interests are in the areas of Microprocessor Architecture, High Performance VLSI design techniques and High Level Testing of VLSI circuits.

C.P. Ravikumar was born in India in 1961. He obtained his Bachelor’s degree in Electronics from Bangalore University, India, in 1983. He received a Masters degree in Computer Science from the Indian Institute of Science in 1987. He obtained a Ph.D. in Computer Engineering from the Department of EE-Systems, University of Southern California, in 1991. Since 1991, he is on the faculty of the Department of Electrical Engineering at the Indian Institute of Technology, Delhi, where he is currently an Associate Professor. He visited the University of Southern California during 1995–1996. Ravikumar serves as the Indian Editor of the International Journal of VLSI Design (Gordon and Breach). He has served on the Program Committees of reputed International Conferences such as the international Conference on VLSI Design, International Conference on High Performance Computing, Parallel and Real-time computing Systems, International Parallel Processing Symposium and Tools for Artificial Intelligence. He is the author of the book Parallel methods for VLSI Physical Design published by Ablex Publishing Corporation, New Jersey, USA. He coordinated a two-week workshop on Recent Advances in testing and Fault-tolerance held at the Indian Institute of Technology, Delhi in 1994. He also coordinated the DRDO-sponsored workshop on Future Directions in VLSI Design and Microelectronics at IIT Delhi in 1996. He was the General Chair for the 2nd International VLSI Design and Test Workshops, New Delhi, 1998.

Gurjeet Saund received his B. Tech. in Electrical Engineering from Indian Institute of Technology in 1995. His B. Tech. Thesis was in the area of Modular and Functional Level Testing of VLSI. He received his MS in Electrical Engineering from the University of Illinois, Urbana Champaign. His Masters Thesis was on Partial Scan selection. He is presently working as a Logic Design Engineer at Chromatic Research Inc. His current areas of interests are computer architecture, VLSI circuit design and testing of VLSI circuits.

View full text