Elsevier

Signal Processing

Volume 81, Issue 4, April 2001, Pages 673-691
Signal Processing

Minimal block processing approach to fractional sample rate conversion

https://doi.org/10.1016/S0165-1684(00)00221-8Get rights and content

Abstract

The problem of synchronous fractional sample rate conversion (FSRC) of a digital signal by L/M, where L and M are coprime integers [6,10], is revisited. Based on a novel approach two different efficient causal block implementations of FSRC are concurrently derived and compared with each other. While the computational load of both structures, being performed in an LTI MIMO subsystem at the subnyquist rate Fo/L=Fi/M, is identical, their group delay is always different. By column and row shifts of the matrix representation of the MIMO subsystem it is possible to transform each structure into any arbitrary implementation with changed group delay. Moreover it is shown that, by structural manipulation of the signal flow graph of the MIMO subsystem, both implementations ultimately require the same amount of computation and storage in spite of different group delay. Finally, by using Nyquist(L)filters, the maximum number of input samples to FSRC is retained at its output.

Zusammenfassung

Das Problem der synchronen Abtastratenumsetzung (FSRC) eines digitalen Signals um den rationalen Faktor L/M, wobei L und M teilerfremd [6,10], wird erneut aufgegriffen. Mit Hilfe eines neuen Ansatzes werden auf systematische Weise nebeneinander zwei effiziente kausale Blockstrukturen zur Implementierung der nichtganzzahligen Abtastratenumsetzung hergeleitet und deren Eigenschaften verglichen. Dabei erfolgt die eigentliche Signalverarbeitung in einem LTI MIMO Teilsystem bei der Abtastrate Fo/L=Fi/M. Obwohl die Gruppenlaufzeit beider Strukturen stets unterschiedlich ist, ist deren Rechenaufwand identisch. Ausgehend von der Matrixdarstellung des MIMO Teilsystems ist es möglich, mit Hilfe von Spalten- und Zeilenverschiebungen jede Struktur in eine beliebige andere mit veränderter Gruppenlaufzeit überzuführen. Ferner wird gezeigt, wie durch strukturelle Manipulation die beiden ursprünglichen Blockstrukturen trotz unterschiedlicher Gruppenlaufzeit mit identischem Gesamtaufwand realisierbar sind. Der Einsatz von Nyquistfiltern (Ltel Band Filter) ermöglicht schließlich, dass die Höchstzahl von Ein- und Ausgangssamples identisch ist.

Introduction

In digitally implemented systems where sampled signals of various, generally to be adapted bandwidths are processed, sample rate conversion is omnipresent. One particular and yet important case of this need of sample rate alteration is the conversion of the sampling rate by a noninteger factor L/M, where L and M are positive and relatively prime integers. The concern of this paper is a novel rigorous derivation of an algorithm and the implementation of this type of sample rate conversion based on block processing with minimum overall expenditure.

The system theoretic approach to fractional sample rate alteration is characterised by the cascade connection of an interpolator for L-fold rate increase followed by a decimator for M-fold rate reduction [5], [17]. The corresponding block structure is depicted in Fig. 1, where the antiimaging filter of the interpolator and the antialiasing filter of the decimator have merged in one filter H(z). As shown in Fig. 1, all filter operations have to be performed at the highest rate F=1/T (T: sampling period), which is related to the system input rate Fi or output rate Fo, respectively, in a fixed synchronous manner byF=LFi=MFo,in compliance with the objective of the fractional sample rate converter:FoFi=LM.

In Fig. 1, the z-domain representations of the input and output signals are related to the respective input and output sampling periods (and rates) [5], [17] according tozi=esTi=esTL=zL,zo=esTo=esTM=zM,where use is made of (1).

By suitably decomposing the highly inefficient structure of Fig. 1 into polyphase components, it is possible to remove all its inherent multiplications with zeros and to perform all arithmetic operations (multiplications and additions) at the subnyquist rateFs=FLM=FiM=FoL,corresponding to the z-domain variablezs=esTLM=zLM=ziM=zoL

A somewhat heuristic derivation of this approach is given in [5], [16], [17]. However, the proposed polyphase structures unfortunately require a multitude of input or output commutators, respectively. These many input or output commutators, respectively, cannot immediately be replaced by one only, since they are interconnected by delay elements being operated at the input or output rate, respectively. Nevertheless, this extra expenditure is superfluous, and it will be shown in this paper how it can be avoided.

A polyphase structure of a fractional sample rate converter that overcomes the above hardware deficiency was revealed in a US-patent [6] and published in three conference papers [7], [9], [10], respectively. This approach requires one input commutator for M-fold decimation, and one output commutator for L-fold sample interleaving. All operations (including any memory shift) are performed at the subnyquist rate Fs. In [6], [7], [9], [10], however, a proper mathematical derivation and, in particular, an exhaustive discussion of the well-defined minimal polyphase structure is missing.

In this paper, two novel systematic and rigorous derivations of two possible optimum polyphase implementations of the above-defined fractional sample rate conversion (FSRC) are developed concurrently. The features and merits of both approaches applying block processing are discussed and compared with each other. The conditions for the minimal implementation are given. Finally, the results are illustrated by an example, and it is shown that both approaches can be implemented with exactly the same amount of hardware.

Section snippets

The minimal polyphase implementation

The derivation of the minimal polyphase implementation of the FSRC starts from Fig. 1. LetH(z)=z−KHc(z),KN0where Hc(z) represents a causal, possibly minimum phase FIR or IIR filter, respectively, suitably specified and designed for FSRC [5], [17]. Due to the extra memory, H(z) is not minimum phase but always causal and, hence, realisable. In course of the polyphase decompositions to follow, the respective minimum values of the quantity KN0={0, 1, 2,…} will be determined.

Example and further discussion

With L=3, M=5 andHc(z)=k=0nhc(k)z−k=k=022hkz−k,we have chosen a simple yet general enough FIR-example to gain maximum insight. Due to the above filter order, all entries of the matrix S(zs) of the L×M LTI MIMO system of Fig. 4 are non-zero, since N=n+1=23>L×M=15. Hence, each path of both cases of Fig. 5 is provided with at least one non-zero coefficient as a result of the twofold polyphase decomposition. We also consider the case of an Lth band filter, where in compliance with (19)hc(n2)=h11=1

Conclusion

In this paper a novel systematic and rigorous 5-step derivation of fractional sample rate conversion (FSRC; Fig. 1) of synchronous sampling frequencies by a fixed ratio L/M is given, where L and M are constrained to be relatively prime integers. The correctness of the algorithms has also been verified by computer simulation using MATLAB. The main features of the described approach to FSRC, elaborated by general investigation (Section 2) and detailed discussion of various examples (Section 3),

Acknowledgements

This work was supported by Deutsche Forschungsgemeinschaft under contract GO 849/1-1.

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