Elsevier

Parallel Computing

Volume 17, Issue 8, October 1991, Pages 941-952
Parallel Computing

Paper
Short Communication
Reconfigurable VLSI/WSI multipipelines

https://doi.org/10.1016/S0167-8191(05)80077-8Get rights and content

Abstract

In supercomputers, pipelines are often used to perform vector operations. These pipelines typically consist of several functionally different stages. One of the problems in implementing such a system on a VLSI chip or wafer is that the probability of having a fault is not negligible. Consequently, it is desirable to have some means of achieving fault tolerance. In this paper, we present a reconfiguration algorithm for multipipelines in the presence of faults. Multipipelines are assumed to be organized in rows and columns. Faulty stages are bypassed using switching elements placed between adjacent stages. Unlike other approaches, the algorithm can cover faults in switching elements as well as faults in stages (or PEs) of multipipelines.

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