A fast hypergraph min-cut algorithm for circuit partitioning
Introduction
Circuit partitioning is a central problem in VLSI system design [1]. A good partitioning tool is required to divide a large system into smaller, more manageable components. As a result, many years of research has been done to develop fast algorithms to find partition solutions of better quality. The development of research in partitioning in the past two decades can be found in a comprehensive survey by Alpert and Kahng [2].
Because of the difference between on-chip and off-chip signal delays, a good partitioning should limit the number of signals travelling off-chip to ensure high system performance. So min-cut partitioning that minimizes the number of interconnections between different chips is desired.
As a net can connect multiple modules, the natural representation for a circuit netlist is a hypergraph where the nodes correspond to the modules and the hyperedges correspond to the interconnections. And the cost of each hyperedge reflects the cost of the corresponding interconnection. There are many algorithms for solving the minimum cut problem for graphs known in the literature [3]. Most of these algorithms rely on maximum flow computations motivated by the famous max-flow min-cut theorem2 by Ford and Fulkerson [4]. More recently, several researchers [5], [6], [7] presented some very efficient algorithms for computing minimum cut without using any flow computation. The fastest algorithms known today are by Nagamochi and Ibaraki [6], and Stoer and Wagner [7]. Their algorithms have a running time of where m is the number of edges and n is the number of nodes in the graph. Unfortunately, these algorithms are designed for finding minimum cuts in graphs but not in hypergraphs.
Some researchers have tried to find ways to model a hypergraphs by a graph. One model often used is the clique-model where each hyperedge is modeled by a clique [8]. (A clique of k nodes is a complete graph with an edge connecting each pair of the k nodes.) Ideally, the cost of cutting the clique anywhere should be equal to the cost of cutting the corresponding hyperedge. Many different cost assignment methods have been proposed, however, none of them can preserve the cut values of different partitions after the transformation. Indeed, Ihler et al. [9] proved that there is no such perfect transformation to model hypergraphs by graphs with the same min-cut properties.3 That means any strategy that relies on hypergraph to graph transformation and the use of a minimum cut algorithm for graphs can at best find approximate solutions to an optimal partition of the hypergraph. But because of the importance of the partitioning problem, we have to seek an optimal algorithm for solving the hypergraph minimum cut problem exactly.
The hypergraph minimum cut problem was studied in [10], [11]. Hu and Moerder first considered the problem in [10]. They modeled each net x as a star node (Fig. 1) in a node-capacitated flow network where each star node has a capacity equals to the cost of the corresponding net and all other nodes have infinite capacity. They presented a simple flow augmenting-type algorithm to compute the minimum node separator of the network. Since any non-star node has infinite capacity, the minimum node separator cannot contain any non-star node. Thus, a minimum node separator must be a subset of the star nodes which corresponds to the set of nets in a minimum cut of the hypergraph. However, the node-capacitated flow network can be readily transformed into an arc-capacitated network using a technique due to Lawler [12]. Fig. 2(a) shows how the star in Fig. 1 is transformed. After transforming to an arc-capacitated network, more efficient flow algorithms can be applied. Later, Yang and Wong [11] presented another transformation technique that uses less nodes and arcs in the resultant flow network. Fig. 2(b) shows how the star in Fig. 1 is transformed using this new technique.
The fastest known algorithms for computing a minimum s–t cut that separates two fixed nodes in a network are flow-based algorithms [3] which takes time where n′ and m′ are the numbers of nodes and arcs in the network. Using the transformation of [11], the network constructed for computing a hypergraph minimum cut has n+2m nodes and m+2p arcs where m, n, and p are the numbers of hyperedges, nodes, and terminals in the hypergraph. So, computing a hypergraph minimum s–t cut using the flow-based approach takes time. We note that a global minimum cut can be found by computing n−1 minimum s–t cuts. (The difference between a global minimum cut and a s–t cut is explained in Section 2.)
However, in this paper, we present a non-flow-based algorithm to compute a global minimum cut in a hypergraph directly. Our algorithm runs in time and it is the fastest hypergraph minimum cut algorithm known today. Note that the number of hyperedges m can be exponential in the number of nodes n in a hypergraph, so computing a global minimum cut using our algorithm is even faster than computing just one minimum s–t cut by the flow-based approach which takes time. Our algorithm is a non-trivial extension of the elegant result by Stoer and Wagner [7] which works for graphs only.
The rest of the paper is organized as follows. Section 2 is the preliminaries. Our main algorithm is presented in Section 3. Then in Section 4, we discuss about the implementation of the algorithm and its complexity. The paper is concluded in Section 5.
Section snippets
Preliminaries
A hypergraph H=(V,E) is defined by its node set V and hyperedge set E. While the edges of a graph connect exactly two nodes each, the hyperedges of a hypergraph can connect two or more nodes each. Fig. 3 shows a weighted hypergraph where there is a weight or cost associated with each hyperedge. The nodes connected by a hyperedge e are called the terminals of e. The hypergraph in Fig. 3 consists of three hyperedges, one of them has nodes a, c, and d as its terminals and has a weight equal to 2.
A
Hypergraph minimum cut algorithm
The algorithm for computing a minimum cut of a hypergraph is based on the following observation. If we have a procedure P that can compute a minimum s–t cut for some nodes s and t quickly for any hypergraph, then we can compute a global minimum cut quickly by using the procedure n−1 times where n is the number of nodes in the hypergraph.
We can find a global minimum cut for a hypergraph with two nodes by applying procedure P once because a minimum s–t cut is also a global minimum cut for a
Implementation and complexity
Let n be the number of nodes in hypergraph H. Let p be the total number of terminals in all the hyperedges of H. The Fast Minimum s–t Cut Algorithm can be implemented to run in time.
In the Fast Minimum s–t Cut Algorithm, we need to keep track of the value of w(A,v) for all node v not in the current set A. And we have to find a node v not in the current A with the maximum w(A,v) value quickly. We can put the nodes into a priority queue using the value of w(A,v) as the key of node v.
Conclusions
Because of the importance of the hypergraph minimum cut problem in finding good partitions for VLSI circuits, many researchers have studied this problem. Previously, the best reported approach to find a minimum cut in a hypergraph requires transforming the hypergraph into a larger flow network and then applying a flow-based algorithm on the network. However, in this paper we presented a more efficient non-flow-based approach to compute a minimum cut in a hypergraph directly. Our algorithm is
Wai-Kei Mak received the B.S. degree in Computer Science from the University of Hong Kong, Hong Kong, China, in 1993. He received the M.S. degree and the Ph.D. degree in Computer Science from the University of Texas at Austin in 1995 and 1998, respectively.
Currently, Dr. Mak is an Assistant Professor in the Computer Science and Engineering Department of the University of South Florida. From 1994 to 1998, he was a research/teaching assistant in the Computer Sciences Department of the University
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Wai-Kei Mak received the B.S. degree in Computer Science from the University of Hong Kong, Hong Kong, China, in 1993. He received the M.S. degree and the Ph.D. degree in Computer Science from the University of Texas at Austin in 1995 and 1998, respectively.
Currently, Dr. Mak is an Assistant Professor in the Computer Science and Engineering Department of the University of South Florida. From 1994 to 1998, he was a research/teaching assistant in the Computer Sciences Department of the University of Texas at Austin. He worked as a CAD engineer at Intel Corporation, Santa Clara, for a summer internship in 1997. His research interests include computer-aided design of VLSI circuits, design automation of multi-FPGA systems, and design and analysis of combinatorial optimization algorithms.
D.F. Wong received the B.Sc. degree in Mathematics from the University of Toronto (Canada) and the M.S. degree in mathematics from the University of Illinois at Urbana-Champaign. He obtained the Ph.D. degree in computer science from the University of Illinois at Urbana-Champaign.
Dr. Wong is currently Professor of Computer Sciences at the University of Texas at Austin. His main research interest is CAD of VLSI. He has published over 200 technical papers and has graduated 22 Ph.D. students in this area. He is a coauthor of “Simulated Annealing for VLSI Design” (Kluwer Academic Publishers, 1988) and two invited articles in the Wiley Enclycopedia of Electrical and Electronics Engineering (1999).
Dr. Wong received the 2000 IEEE CAD Transactions Best Paper Award for his work on interconnect optimization. He also received best paper awards at DAC-86 and ICCD-95 for his work on floorplan design and FPGA routing, respectively. Dr. Wong was the General Chair of the 1999 ACM International Symposium on Physical Design (ISPD-99) and was the Technical Program Chair of the same conference in 1998 (ISPD-98). He also has served on the technical program committees of many other VLSI CAD conferences (e.g., ICCAD, ISPD, DATE, ISCAS, FPGA). Dr. Wong has served as an Associate Editor for IEEE Transactions on Computers and Guest Editor of two special issues on physical design for IEEE Transactions on Computer-Aided Design. He is on the Editorial Boards of ACM Transactions on Design Automation of Electronic Systems and International Journal on Applied Mathematics.
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The work of this author was partially supported by the National Science Foundation under grant CCR-9912390 and by the Texas Advanced Research Program under Grant No. 003658288.