Elsevier

Integration

Volume 31, Issue 1, November 2001, Pages 65-77
Integration

Floorplanning with abutment constraints based on corner block list

https://doi.org/10.1016/S0167-9260(01)00022-0Get rights and content

Abstract

Corner Block List (CBL) was recently proposed as an efficient representation of general rectangle packing: different from other topological representations, CBL needs a smaller amount of encoding storage and linear time computation effort to generate each placement configuration. To extend its applicability to simple rectangle packings, this paper addresses the problem of handling abutment constraints in the context of the CBL representation. We can obtain the abutment information by scanning the intermediate solutions represented by CBL in linear time during the simulated annealing process and fix the CBL by the heuristic method in case the constraints are violated. A novel penalty function is derived to measure the violation of the abutment constraints and help to ensure all the constraints are satisfied at the end of the annealing process. The experimental results are demonstrated by several examples of MCNC benchmarks and the performance shows the effectiveness of the proposed method.

Introduction

A good floorplanner must not only provide a good rectangle packing functionality but also the flexibility to handle a large variety of specific constraints. The VLSI floorplans are often grouped into two classes: slicing and non-slicing. A slicing floorplan is a floorplan which can be obtained by recursively cutting a rectangle into two parts by either a vertical line or a horizontal line. A non-slicing floorplan is one not restricted to be slicing. The slicing floorplan can be expressed by an oriented rooted binary tree named slicing tree [1]. For general floorplan including both slicing and non-slicing, several encoding schemes were recently proposed, namely, Sequence-Pair(SP) [2], Bound-Sliceline-Grid(BSG) [3], O-tree [4], B*-tree [5] and Corner Block List(CBL) [6], [7]. All of them except O-tree and B*-tree employ topological representations of placement configurations, where cell positions are specified based on encoded topological relations. The CBL is an effective representation: different from other topological representations, CBL needs a smaller amount of encoding storage and linear time computation effort to generate each placement configuration. These advantages are good for handling placement constraints in general.

The abutment constraint problem is one of the common constraints in practice for the designer may want to have the logic blocks in a pipeline of a circuit to abut one after another to favor the transmission of data between them. But in most stochastic floorplanning algorithms, the relative position between two blocks is not known until the exact dimensions of blocks are taken into account. Though BSG and SP can represent non-slicing structure effectively, the relative positions between two modules are affected by the dimensions of all the other modules lying to the left or below those two modules. It is a non-trival problem to control the relative position of an arbitrary number of modules by using SP and BSG. Recently, Young [8] has proposed the algorithm to handle abutment constraints based on slicing structure. But the algorithm in Ref. [8] cannot ensure that all the constraints are satisfied in the final floorplan. We propose a new abutment constraint algorithm based on CBL which can handle the abutment constraints for both slicing and non-slicing. In our algorithm, we check the abutment constraints by scanning the intermediate solutions represented by CBL in linear time during the simulated annealing process and fix the CBL in case the constraints are violated. A penalty function is derived to measure the violation of the abutment constraints and help to ensure that all the constraints are satisfied at the end of the annealing process. Our algorithm has been implemented in C language and the experimental results are promising.

The rest of the paper is composed as follows: A formal definition of abutment constraint is described in Section 2. Section 3 is a brief review of the CBL model. The new algorithm is presented in Section 4. The experimental results are shown in Section 5. Finally, the conclusion is given.

Section snippets

Problem definition

In floorplanning, each rectangular block Mi is defined by a tuple(hi,wi), where hi and wi are the height and the width of the block Mi, respectively. The aspect ratio of Mi is defined as hi/wi. There are two kinds of rectangular blocks: soft blocks and hard blocks. The soft blocks have fixed area with variable aspect ratio within a given range. The hard blocks have fixed area and aspect ratio. Since the multiformity of the soft blocks magnifies the solution space greatly, the floorplan problem

Corner block list

A floorplan divides the chip into rectangular rooms with horizontal and vertical segments. Each room is assigned to no more than one block. Each pair of intersected segments forms a T-junction. A T-junction is composed of two segments: a non-crossing segment and a crossing segment. The non-crossing segment has one end touching point in the interval of the crossing segment. CBL is derived from a simplified version of general floorplan called mosaic floorplan. A floorplan belongs to the class of

Abutment constraints over CBL

Abutment information is embodied in the blocks beside the segments, which divides the chip into rectangular rooms: the blocks beside a horizontal segment abut vertically; the blocks beside a vertical segment abut horizontally. Each block has four boundaries to abut with other blocks.

Definition 3

HSEG is one horizontal segment and thus THSEGh and BHSEGh denote the sets of blocks lying above and below segment HSEG, respectively; VSEG is one vertical segment and thus LVSEGv and RVSEGv denote the sets of blocks

Experimental results

The floorplan algorithm with abutment constraints has been implemented in the C programming language, and all experiments are performed on a SUN spark20 workstation. Some MCNC benchmarks are used for the examples. To test the efficiency of our algorithm with larger scale floorplanning problem, we expand ami33 and ami49 to compose P_65, P_99 and P_147 which have 65 modules, 99 modules and 147 modules, respectively. All the blocks in the experiments have shape flexibility that their aspect ratios

Summary and conclusions

This paper proposes a new algorithm to handle the abutment constraints not only with slicing structure, but also with non-slicing structure. Our algorithm runs in O(n) time, where n is the number of the blocks. The penalty terms devised in this paper evaluate the violations of the constraints accurately, thus it is ensured that all the abutment constraints are satisfied in the final results. The experimental results demonstrate that our algorithm is quite promising.

Yuchun Ma received B.S. degree in Computer Science from Xi’an Jiaotong University in 1999 and she is currently a Ph.D. candidate of the Department of Computer Science and Technology, Tsinghua University, Beijing, People's Republic Of China. Her research interests includes algorithms for VLSI automation design, especially floorplanning.

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Yuchun Ma received B.S. degree in Computer Science from Xi’an Jiaotong University in 1999 and she is currently a Ph.D. candidate of the Department of Computer Science and Technology, Tsinghua University, Beijing, People's Republic Of China. Her research interests includes algorithms for VLSI automation design, especially floorplanning.

Xianlong Hong graduated from Tsinghua University, Beijing, China in 1964. Since 1988, he has been a professor in the Department of Computer Science and Technology, Tsinghua University. His research interests include VLSI layout algorithms and DA systems. He is the Senior Member of IEEE and Chinese Institute of Electronics.

Sheqin Dong received the B.S. degree (highest honors) in Computer Science in 1985, M.S. degree in semiconductor physics and device in 1988, and Ph.D. degree in mechantronic control and automation in 1996, all from Harbin Institute of Technology. From 1997 to 1999, he worked as a postdoctoral fellow in The State Key Lab. of CAD&CG in Zhejiang University. He is currently an Associate Professor at the Department of Computer Science and Technology of Tsinghua University. His current research interests include CAD for VLSI, parallel algorithms, multi-media ASIC and hardware design.

Yici Cai received B.S degree from Tsinghua University in 1983 and M.S degree from Tsinghua University in 1986, she has been an associate professor in the Department of Computer Science and Technology, Tsinghua University. Beijing, China. Her research interests include VLSI layout.

Chung-Kuan Cheng received the B.S. and M.S. degrees in Electrical Engineering from the National Taiwan University, Taiwan, and the Ph.D. degree in Electrical Engineering and computer science from the University of California, Berkeley, in 1984. His research interests include network optimization and design automation on microelectronic circuits. Dr. Cheng has been an Associate Editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems since 1994. He was awarded Fellow of IEEE in 2000.

Jun Gu received B.S degree in Electrical Engineering from the University of Science and Technology of China in 1982 and Ph.D degree in Computer Science from the University of Utah in 1989. He was the professor of Calgary University in Canada and is currently the professor of the Department of Computer Science in Hong Kong University of Science and Technology. His research interests include the optimization algorithms, local search and global optimization, and their application in VLSI CAD, system engineering, communication and multi-media fields. He is the chief scientist of the 973 Key Foundation Research and Development Project “The Application Theories and High Performance Software in Information Technology” in China. Dr. Gu is a member of the ACM, AAAI, International Neural Network Society, and Sigma Xi.

This work is supported by National Science Foundation (No. 60076016) and 973 National Key Project (No.G1998030411)

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