Low-power VLSI synthesis of DSP systems
Introduction
Recently, reduction of power consumption has become a very critical issue in the design of high-performance VLSI synthesis of DSP systems. The techniques used to achieve reduced power consumption range from algorithmic and architectural levels to gate, switch and device levels. In this paper, we propose low-power algorithmic and architectural design methodologies for several signal-processing systems. There are several approaches for power reduction in high-speed VLSI implementations. Pipelining and parallel processing can be combined for lower power consumption; where pipelining reduces the capacitance to be charged/discharged in one clock period, while parallel processing increases the clock period for charging/discharging the original capacitance. Both pipelining and parallelism can therefore be used to reduce power consumption by reducing the supply voltage. Power consumption can be reduced by reducing the number of gates or by algorithmic strength reduction, where the number of operations in an algorithm is reduced. Reducing the memory accesses can also reduce power consumption. The most effective clock gating technique of reducing power consumption switches-off the functional units that do not compute any useful outputs by using gated clocks [1]. The power reduction approaches proposed in this paper apply to dedicated or FPGA systems.
Designing low-power decoders has become crucial in modern spread-spectrum wireless communication systems. Code division multiple access (CDMA) spread-spectrum technology was introduced in the second generation of mobile systems, and was shown to be the technology for third-generation mobile systems [2]. In CDMA systems, the Viterbi decoder (VD) consumes about one-third of the power dissipation, which is used to optimally decode convolutional codes. In this work, the algorithmic approach is adopted to design a low-power VD with the focus on minimizing the number of operations [3], [4]. Usually, two methods are adopted to realize the Viterbi algorithm; the register-exchange (RE) and the trace-back (TB) method. In the literature, the RE technique is acceptable only for small state trellis structures, whereas the TB approach is acceptable for large state trellis structures (the number of states in CDMA systems is 256). In Section II of this paper, a novel approach to implement the RE method is proposed, which makes it feasible for use with large constraint length VDs, in addition to being simpler and lower in power consumption than the TB method.
FIR filtering is another important operation in DSP systems. In high-performance digital VLSI implementations, FIR filters often require long lengths or large number of taps. An implementation, where every multiply-add operation is mapped to a multiplier-adder in hardware, becomes prohibitively area expensive. Therefore, for area-efficient FIR filters, folding or time multiplexing is used to map multiple algorithm operations (multiplication and addition operations) on a single functional unit, resulting in saving of the silicon area. Unfortunately, maximal resource sharing while minimizing area can lead to a large increase in power consumption. In Section III of the paper, we propose a low-power technique for designing folded FIR filters where storage area is traded-off for reducing power consumption. The paper is concluded in Section IV.
Section snippets
Low power design of Viterbi decoder
In 1967, Viterbi developed the Viterbi algorithm (VA) to decode the convolutional codes to the optimum level [5], [6]. A simple convolutional encoder with K=3 with code rate 1/3, and the generator polynomials G0=58, G1=78 and G2=78, has the trellis diagram shown in Fig. 1. A sample input data to the encoder are tracked until they are decoded at the decoder. The encoder encodes the input sequence (1011010) and generates the codeword (111,011,000,100,100,000,011). This stream is transmitted over
Low power folded FIR filter
Folding [12] is a technique to reduce silicon area by time-multiplexing many algorithm operations into single functional units (such as adders and multipliers). This technique ensures efficient resource sharing for area-constrained behavioral synthesis from a data flow graph (DFG). The throughput requirement in folded architectures is achieved by pipelining the hardware functional units to an appropriate level. In this manner, folded architectures can be used to meet both throughput and
Conclusion
Several power-reduction approaches are proposed in the high-level VLSI synthesis of DSP systems. An algorithmic approach is proposed with the aim of minimizing the number of algorithm operations to reduce power consumption in VLSI implementation of Vietrbi decoder. It has been shown that appropriate unfolding and transpose forms of FIR filter structures can lead to reduction of power by reducing switching activity. The technique employed gives a formal approach to an intuitive notion that
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