An architecture for a VLSI FFT processor

doi:10.1016/S0167-9260(83)80004-2

Integration

Volume 1, Issue 4, December 1983, Pages 305-316

https://doi.org/10.1016/S0167-9260(83)80004-2 Get rights and content

Abstract

We propose a new VLSI architecture for an FFT processor. Our architecture uses few processing elements and can be laid out in a mesh-interconnected pattern. We show how to compute the discrete Fourier transform at n points with an optimal speed-up as long as the memory is large enough. The control is shown to be simple and easily implementable in VLSI.

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There are more references available in the full text version of this article.

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^*: This research has been supported by the U.S. Army Research Office, Contract No. DAAG29-82-K-0110 and U.S. Office of Naval Research, Contract No. N00014-80-C-0517.

^**: Now with the Department of Electrical Engineering, University of Maryland, College Park, MD 20742, U.S.A.

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An architecture for a VLSI FFT processor*

Abstract

The chip complexity of binary arithmetic

An algorithm for the machine calculation of complex Fourier series

Math. Comput.

Very fast Fourier transform algorithms for hardware implementation

IEEE Trans Comput.

VLSI implementation of digital Fourier transforms

A model of computation for VLSI with related complexity results

VLSI complexity with reduced hardware

VLSI sorting with reduced hardware