Retiming: Theory and practice
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FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm
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2004, NeurocomputingCitation Excerpt :The reduced number of inputs do not invoke the somewhat poorer performance of this architecture as the number of inputs is increased, that is, as the number of levels in the tree increases. This section explores the use of retiming [6,13] when applied to a registered design. Retiming can decrease the clock period of a design by moving combinational logic through registers.
Hardware-software partitioning and pipelined scheduling of transformative applications
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