An optimal solution for ATM switches

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Abstract

This paper addresses some issues related to the performances and feasibility of an interconnection optical bus for switching boards into large ATM switches. After providing a survey of several solutions to interconnect switching boards, the study presents the advantages of an interconnection by means of a bus. This solution makes it possible to increase the capacity of these switches in terms of global throughput (i.e. number of 155 or 622 Mb/s input/output ports). At the same time, we analyze the advantages of an optical bus for transmission and broadcast of ATM cells between switching boards. This article shows that a shared bus, used in the BSS switch element, provides a good solution for interconnecting an arbitrary number of cards, by optimizing the number of input ports. For this switching element architecture, the study of the interconnection shows that this solution yields better performances than the usual Clos network interconnection.

Introduction

The purpose of the present study is to propose a method for building a large structure by interconnecting switching boards. Section 2presents a brief overview of a few typical ATM switch architectures [1]. Industrial switches available on the market offer a global throughput of about 5 Gb/s 8, 3. Prototypes currently being developed aim to provide throughput of about 100 Gb/s 4, 12. The BSS architecture [5], proposed by Fayet in 1991, offers a throughput of 14 Gb/s for each switching module.

Throughout this paper, the term `functional module' (switching module, interconnection module, …) refers to all the components or elements which ensure this function (switching function, interconnection function, …). The generic term `module' is used for a set of functional modules, located on a single card (or board). These cards, referred to as `switching cards', are interconnected by means of a link set located on a `backplane board'.

Section 3demonstrates that the interboard bitrate must be around 35 Gbit/s in order to reach switching capacities around 256 ports at 155 Mbit/s. Should the basic multiplex carry 622 Mbit/s, this bitrate ought to be about 140 Gbit/s.

This section addresses the two main issues related to the design of such high capacity switches. Firstly, the process used to route the cells from one board to another is presented. Secondly, the architecture of the interboard connection links is evaluated and discussed. A comparative performance study of Clos networks, daisy chain and ring interconnection topologies highlights the advantages of a bus interconnection architecture. With this solution, we demonstrate that the global throughput of a board is strictly independent of their number. The performances of optical buses in terms of bitrate make such an architecture possible [6]. In Section 4, we study how to adapt the architecture of BSS switch elements with regards to their interconnection. We show that such an architecture is very adapted to build an expandable switch. On the one hand, incoming ports, on the other, the switching and interconnection throughput can be calculated so that they are independent of the number of switching cards.

Section snippets

Interconnection: A bottleneck

Currently available ATM switches, rely on fairly different architectures, and offer overall capacities of about 2.5 Gb/s to 5 Gb/s. Only the Cabletron SmartCellSwitch will soon promise a global throughput of 75.6 Gb/s.

The global throughput is the result of the single port bitrate — here, 155 Mbit/s — multiplied by the number of such ports. Although the technical solutions vary from one switch to the other, all realizations exhibit roughly the same throughput, say between 2 and 5 Gbit/s.

All the

A taxonomy of interconnection solutions

Interconnection topologies may be classified into two different categories, each of them raising specific technological issues.

  • Point-to-point interconnections:

    • – by Clos networks;

    • – by daisy chain;

    • – by ring;

  • Multipoint interconnections:

    • – buses.

Module interconnection must provide some means for routing cells from one card to another. The VCI/VPI field makes it possible to retrieve the output port, but it provides no information about the actual path inside the switch, especially the identify of the

Interconnection architecture

The shared bus architecture of this switch is well suited to module interconnection. The BSS switch element can process up to 90 inputlines for a polling cycle of 30 ns (135 inputlines for 20 ns cycle) in the same slot. In this study, all the results are provided for a polling cycle of 30 ns. Moreover, this switching module is able to write more than one cell in an output buffer, during a single slot. The architecture in Fig. 12 shows the interconnection from one switching module to another.

The

Conclusion

In order to increase the switching capabilities of ATM switches, it is necessary to make use of architectures interconnecting basic modules. In this way, the interconnecting bus offers better performances than a standard Clos network in terms of global bitrate and number of links. The BSS shared-bus architecture, modified for interconnection by bus, provides a switching capacity up to 10 Gb/s. Jointed with optical bus interconnections, it meets the main ATM traffic requirements (10−9 cell loss,

Acknowledgements

We would like to thank G. Hebuterne, head of Network and Services Department, INT, for his precious advice.

Dominique Présent joined the University of Marne la Vallée, France, in 1994, where he is actually head of Department Communications Networks and Services. He received the Ph.D. from the University of Versailles St-Quentin en Yvelines, France, in 1996. Recently, he joined INT's Telecommunications Networks and Services research team. He is the author of a book on Transmission and Networks.

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Dominique Présent joined the University of Marne la Vallée, France, in 1994, where he is actually head of Department Communications Networks and Services. He received the Ph.D. from the University of Versailles St-Quentin en Yvelines, France, in 1996. Recently, he joined INT's Telecommunications Networks and Services research team. He is the author of a book on Transmission and Networks.

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Caroline Fayet, D.E.A., Ph.D. thesis, Professor, Department of Telecommunications Networks and Services (INT).

Caroline Fayet's educational background lies in the field of computer science and ATM switching architecture. She entered France Telecom in 1972 where she was appointed as a lecturer with the French Telecommunications School Group. From 1981 to 1990 she was the project leader of the curriculum design in Computer Sciences for the Telecommunications School Group. Since 1990 she has been involved more specifically in research concerning broadband networks and ATM switching. She is currently head of the `Broadband Networks' division at INT and member of the PRISM Laboratory.

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Guy Pujolle received the Ph.D and `Thèse d'Etat' degrees in computer science from the University of Paris IX and Paris XI on 1975 and 1978 respectively. He is currently a professor at the University of Versailles, a member of the PRiSM Laboratory and chairman of the scientific committee of the scientific part of the University of Versailles. Before he was professor at the University of Paris VI and head of the MASI Laboratory depending on the CNRS (Centre National de la Recherche Scientifique), 1981–1993. Before that he was professor at ENST (Ecole National Supérieure de Télécommunications), 1979–1981, and member of the scientific staff of INRIA (Institut National de la Recherche en Informatique et Automatique), 1974–1979.

He is chairman of the IFIP WG 6.4 on `high-performance networking' and a member of the IFIP WG 7.3 on `performance evaluation'. He is also a member of the scientific committee of France Télécom (France), GMD (Germany), CRIM (Canada) and chairman of the Telecommunication Regulation Expert Committee at the French Telecom Ministry.

His research interests include the analysis and modelling of data communication systems, protocols, high performance networking and satellite networks. He is the author of several books and of many papers on diverse aspects of performance analysis and data communication networks.

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